Full Speed USB Flash MCU Family
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 3/19 Copyright © 2019 by Silicon Laboratories C8051F380/1/2/3/4/5/6/7/C
Analog Peripherals
-
10-Bit ADC (C8051F380/1/2/3/C only)
• Up to 500 ksps
• Built-in analog multiplexer with single-ended and
differential mode
• VREF from external pin, internal reference, or V
DD
• Built-in temperature sensor
• External conversion start input option
- Two comparators
- Internal voltage reference (C8051F380/1/2/3/C only)
- Brown-out detector and POR Circuitry
USB Function Controller
-
USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps) operation
- Integrated clock recovery; no external crystal required for
full speed or low speed
- Supports eight flexible endpoints
- 1 kB USB buffer memory
- Integrated transceiver; no external resistors required
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
-
Voltages from 2.7 to 5.25 V supported using On-Chip
Voltage Regulators
High Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 48 MIPS operation
- Expanded interrupt handler
Memory
-
4352 or 2304 Bytes RAM
- 64, 32, or 16 kB Flash; In-system programmable in
512-byte sectors
Digital Peripherals
-
40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, two I
2
C/SMBus™, and two
enhanced UART serial ports
- Six general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five cap-
ture/compare modules
- External Memory Interface (EMIF)
Clock Sources
-
Internal Oscillator: ±0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
- External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
- Low Frequency (80 kHz) Internal Oscillator
- Can switch between clock sources on-the-fly
Packages
-
48-pin TQFP (C8051F380/2/4/6)
- 32-pin LQFP (C8051F381/3/5/7/C)
- 5x5 mm 32-pin QFN (C8051F381/3/5/7/C)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
10-bit
500 ksps
ADC
64/32 kB
ISP FLASH
4/2 kB RAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
48 MIPS
DIGITAL I/O
PRECISION INTERNAL
OSCILLATORS
HIGH-SPEED CONTROLLER CORE
A
M
U
X
CROSSBAR
+
-
WDT
+
-
USB Controller /
Transceiver
Port 0
Port 1
Port 2
Port 3
TEMP
SENSOR
VREG
VREF
Port 4
Ext. Memory I/F
48 Pin Only
UART0
SMBus0
PCA
6 Timers
SPI
UART1
C8051F380/1/2/3 Only
SMBus1
C8051F380/1/2/3/4/5/6/7/C
2 Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 3
Table of Contents
1. System Overview..................................................................................................... 16
2. C8051F34x Compatibility ........................................................................................ 20
2.1. Hardware Incompatibilities ................................................................................ 21
3. Pinout and Package Definitions ............................................................................. 22
4. Typical Connection Diagrams ................................................................................ 34
4.1. Power ............................................................................................................ 34
4.2. USB ............................................................................................................ 36
4.3. Voltage Reference (VREF)................................................................................ 36
5. Electrical Characteristics........................................................................................ 37
5.1. Absolute Maximum Specifications..................................................................... 37
5.2. Electrical Characteristics ................................................................................... 38
6. 10-Bit ADC (ADC0, C8051F380/1/2/3/C only) ......................................................... 46
6.1. Output Code Formatting.................................................................................... 47
6.3. Modes of Operation........................................................................................... 50
6.3.1. Starting a Conversion................................................................................ 50
6.3.2. Tracking Modes......................................................................................... 51
6.3.3. Settling Time Requirements...................................................................... 52
6.4. Programmable Window Detector....................................................................... 56
6.4.1. Window Detector Example........................................................................ 58
6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C only)........................................ 59
7. Voltage Reference Options..................................................................................... 62
8. Comparator0 and Comparator1.............................................................................. 64
8.1. Comparator Multiplexers ................................................................................... 71
9. Voltage Regulators (REG0 and REG1)................................................................... 74
9.1. Voltage Regulator (REG0)................................................................................. 74
9.1.1. Regulator Mode Selection......................................................................... 74
9.1.2. VBUS Detection........................................................................................ 74
9.2. Voltage Regulator (REG1)................................................................................. 74
10. Power Management Modes................................................................................... 76
10.1. Idle Mode......................................................................................................... 76
10.2. Stop Mode....................................................................................................... 77
10.3. Suspend Mode ................................................................................................ 77
11. CIP-51 Microcontroller........................................................................................... 79
11.1. Instruction Set........................................
.......................................................... 80
11.1.1. Instruction and CPU Timing .................................................................... 80
11.2. CIP-51 Register Descriptions .......................................................................... 85
12. Prefetch Engine...................................................................................................... 88
13. Memory Organization............................................................................................ 89
13.1. Program Memory............................................................................................. 91
13.2. Data Memory................................................................................................... 91
13.3. General Purpose Registers ............................................................................. 92
13.4. Bit Addressable Locations............................................................................... 92
13.5. Stack ............................................................................................................ 92
C8051F380/1/2/3/4/5/6/7/C
4 Rev. 1.5
14. External Data Memory Interface and On-Chip XRAM......................................... 93
14.1. Accessing XRAM............................................................................................. 93
14.1.1. 16-Bit MOVX Example ............................................................................ 93
14.1.2. 8-Bit MOVX Example.............................................................................. 93
14.2. Accessing USB FIFO Space ........................................................................... 94
14.3. Configuring the External Memory Interface..................................................... 95
14.4. Port Configuration............................................................................................ 95
14.5. Multiplexed and Non-multiplexed Selection..................................................... 98
14.5.1. Multiplexed Configuration........................................................................ 98
14.5.2. Non-multiplexed Configuration................................................................ 98
14.6. Memory Mode Selection................................................................................ 100
14.6.1. Internal XRAM Only .............................................................................. 100
14.6.2. Split Mode without Bank Select............................................................. 100
14.6.3. Split Mode with Bank Select.................................................................. 101
14.6.4. External Only......................................................................................... 101
14.7. Timing .......................................................................................................... 102
14.7.1. Non-multiplexed Mode.......................................................................... 104
14.7.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 104
14.7.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111....... 105
14.7.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 106
14.7.2. Multiplexed Mode.................................................................................. 107
14.7.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 107
14.7.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011....... 108
14.7.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 109
15. Special Function Registers................................................................................. 111
15.1. 13.1. SFR Paging .......................................................................................... 111
16. Interrupts.............................................................................................................. 118
16.1. MCU Interrupt Sources and Vectors.............................................................. 119
16.1.1. Interrupt Priorities.................................................................................. 119
16.1.2. Interrupt Latency................................................................................... 119
16.2. Interrupt Register Descriptions...................................................................... 119
16.3. INT0 and INT1 External Interrupt Sources.................................................... 127
17. Reset Sources...................................................................................................... 129
17.1. Power-On Reset............................................................................................ 130
17.2. Power-Fail Reset / VDD Monitor ................................................................... 131
17.3. External Reset............................................................................................... 132
17.4. Missing Clock Detector Reset ....................................................................... 132
17.5. Comparator0 Reset ....................................................................................... 132
17.6. PCA Watchdog Timer Reset ......................................................................... 133
17.7. Flash Error Reset .......................................................................................... 133
17.8. Software Reset.............................................................................................. 133
17.9. USB Reset..................................................................................................... 133
18. Flash Memory....................................................................................................... 135
18.1. Programming The Flash Memory.................................................................. 135
18.1.1. Flash Lock and Key Functions.............................................................. 135
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 5
18.1.2. Flash Erase Procedure ......................................................................... 135
18.1.3. Flash Write Procedure .......................................................................... 136
18.2. Non-Volatile Data Storage............................................................................. 137
18.3. Security Options............................................................................................ 137
19. Oscillators and Clock Selection......................................................................... 142
19.1. System Clock Selection................................................................................. 143
19.2. USB Clock Selection ..................................................................................... 143
19.3. Programmable Internal High-Frequency (H-F) Oscillator.............................. 145
19.3.1. Internal Oscillator Suspend Mode......................................................... 145
19.4. Clock Multiplier .............................................................................................. 147
19.5. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 148
19.5.1. Calibrating the Internal L-F Oscillator.................................................... 148
19.6. External Oscillator Drive Circuit..................................................................... 149
19.6.1. External Crystal Mode........................................................................... 149
19.6.2. External RC Example............................................................................ 151
19.6.3. External Capacitor Example.................................................................. 151
20. Port Input/Output................................................................................................. 153
20.1. Priority Crossbar Decoder ............................................................................. 154
20.2. Port I/O Initialization ...................................................................................... 158
20.3. General Purpose Port I/O.............................................................................. 161
21. Universal Serial Bus Controller (USB0)............................................................. 172
21.1. Endpoint Addressing ..................................................................................... 172
21.2. USB Transceiver ........................................................................................... 173
21.3. USB Register Access.................................................................................... 175
21.4. USB Clock Configuration............................................................................... 179
21.5. FIFO Management ........................................................................................ 181
21.5.1. FIFO Split Mode.................................................................................... 181
21.5.2. FIFO Double Buffering .......................................................................... 182
21.5.1. FIFO Access ......................................................................................... 182
21.6. Function Addressing...................................................................................... 183
21.7. Function Configuration and Control............................................................... 183
21.8. Interrupts ....................................................................................................... 186
21.9. The Serial Interface Engine........................................................................... 193
21.10. Endpoint0 .................................................................................................... 193
21.10.1. Endpoint0 SETUP Transactions .........................................................
193
21.10.2. Endpoint0 IN Transactions.................................................................. 193
21.10.3. Endpoint0 OUT Transactions.............................................................. 194
21.11. Configuring Endpoints1-3............................................................................ 196
21.12. Controlling Endpoints1-3 IN......................................................................... 197
21.12.1. Endpoints1-3 IN Interrupt or Bulk Mode.............................................. 197
21.12.2. Endpoints1-3 IN Isochronous Mode.................................................... 198
21.13. Controlling Endpoints1-3 OUT..................................................................... 201
21.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode.......................................... 201
21.13.2. Endpoints1-3 OUT Isochronous Mode................................................ 201
22. SMBus0 and SMBus1 (I2C Compatible)............................................................. 205
C8051F380/1/2/3/4/5/6/7/C
6 Rev. 1.5
22.1. Supporting Documents.................................................................................. 206
22.2. SMBus Configuration..................................................................................... 206
22.3. SMBus Operation .......................................................................................... 206
22.3.1. Transmitter Vs. Receiver....................................................................... 207
22.3.2. Arbitration.............................................................................................. 207
22.3.3. Clock Low Extension............................................................................. 207
22.3.4. SCL Low Timeout.................................................................................. 207
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 208
22.4. Using the SMBus........................................................................................... 208
22.4.1. SMBus Configuration Register.............................................................. 208
22.4.2. SMBus Timing Control Register............................................................ 210
22.4.3. SMBnCN Control Register .................................................................... 214
22.4.3.1. Software ACK Generation ............................................................ 214
22.4.3.2. Hardware ACK Generation........................................................... 214
22.4.4. Hardware Slave Address Recognition .................................................. 217
22.4.5. Data Register ........................................................................................ 221
22.5. SMBus Transfer Modes................................................................................. 223
22.5.1. Write Sequence (Master) ...................................................................... 223
22.5.2. Read Sequence (Master)...................................................................... 224
22.5.3. Write Sequence (Slave) ........................................................................ 225
22.5.4. Read Sequence (Slave)........................................................................ 226
22.6. SMBus Status Decoding................................................................................ 226
23. UART0................................................................................................................... 232
23.1. Enhanced Baud Rate Generation.................................................................. 233
23.2. Operational Modes........................................................................................ 234
23.2.1. 8-Bit UART............................................................................................ 234
23.2.2. 9-Bit UART............................................................................................ 235
23.3. Multiprocessor Communications ................................................................... 236
24. UART1................................................................................................................... 240
24.1. Baud Rate Generator .................................................................................... 241
24.2. Data Format................................................................................................... 242
24.3. Configuration and Operation ......................................................................... 243
24.3.1. Data Transmission ................................................................................ 243
24.3.2. Data Reception ..................................................................................... 243
24.3.3. Multiprocessor Communications..................................
......................... 244
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 250
25.1. Signal Descriptions........................................................................................ 251
25.1.1. Master Out, Slave In (MOSI)................................................................. 251
25.1.2. Master In, Slave Out (MISO)................................................................. 251
25.1.3. Serial Clock (SCK) ................................................................................ 251
25.1.4. Slave Select (NSS) ............................................................................... 251
25.2. SPI0 Master Mode Operation........................................................................ 251
25.3. SPI0 Slave Mode Operation.......................................................................... 253
25.4. SPI0 Interrupt Sources.................................................................................. 254
25.5. Serial Clock Phase and Polarity .................................................................... 254
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 7
25.6. SPI Special Function Registers..................................................................... 256
26. Timers................................................................................................................... 263
26.1. Timer 0 and Timer 1 ...................................................................................... 266
26.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 266
26.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 267
26.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 267
26.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 268
26.2. Timer 2 .......................................................................................................... 274
26.2.1. 16-bit Timer with Auto-Reload............................................................... 274
26.2.2. 8-bit Timers with Auto-Reload............................................................... 275
26.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ..... 275
26.3. Timer 3 .......................................................................................................... 281
26.3.1. 16-bit Timer with Auto-Reload............................................................... 281
26.3.2. 8-bit Timers with Auto-Reload............................................................... 282
26.3.3. Timer 3 Capture Modes: USB Start-of-Frame or LFO Falling Edge ..... 282
26.4. Timer 4 .......................................................................................................... 288
26.4.1. 16-bit Timer with Auto-Reload............................................................... 288
26.4.2. 8-bit Timers with Auto-Reload............................................................... 289
26.5. Timer 5 .......................................................................................................... 293
26.5.1. 16-bit Timer with Auto-Reload............................................................... 293
26.5.2. 8-bit Timers with Auto-Reload............................................................... 294
27. Programmable Counter Array............................................................................. 298
27.1. PCA Counter/Timer ....................................................................................... 299
27.2. PCA0 Interrupt Sources................................................................................. 300
27.3. Capture/Compare Modules ........................................................................... 301
27.3.1. Edge-triggered Capture Mode............................................................... 302
27.3.2. Software Timer (Compare) Mode.......................................................... 303
27.3.3. High-Speed Output Mode ..................................................................... 304
27.3.4. Frequency Output Mode ....................................................................... 305
27.3.5. 8-bit Pulse Width Modulator Mode....................................................... 306
27.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 307
27.4. Watchdog Timer Mode .................................................................................. 308
27.4.1. Watchdog Timer Operation................................................................... 308
27.4.2. Watchdog Timer Usage ........................................................................ 309
27.5. Register Descriptions for PCA0..............................................
....................... 311
28. C2 Interface .......................................................................................................... 316
28.1. C2 Interface Registers................................................................................... 316
28.2. C2 Pin Sharing .............................................................................................. 319
Document Change List.............................................................................................. 320
Contact Information................................................................................................... 321
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 8
List of Figures
Figure 1.1. C8051F380/2/4/6 Block Diagram .......................................................... 18
Figure 1.2. C8051F381/3/5/7/C Block Diagram ....................................................... 19
Figure 3.1. TQFP-48 Pinout Diagram (Top View) ................................................... 25
Figure 3.2. TQFP-48 Package Diagram .................................................................. 26
Figure 3.3. TQFP-48 Recommended PCB Land Pattern ........................................ 27
Figure 3.4. LQFP-32 Pinout Diagram (Top View) .................................................... 28
Figure 3.5. LQFP-32 Package Diagram .................................................................. 29
Figure 3.6. LQFP-32 Recommended PCB Land Pattern ........................................ 30
Figure 3.7. QFN-32 Pinout Diagram (Top View) ..................................................... 31
Figure 3.8. QFN-32 Package Drawing .................................................................... 32
Figure 3.9. QFN-32 Recommended PCB Land Pattern .......................................... 33
Figure 4.1. Connection Diagram with Voltage Regulator Used and No USB .......... 34
Figure 4.2. Connection Diagram with Voltage Regulator Not Used and No USB ... 34
Figure 4.3. Connection Diagram with Voltage Regulator Used and USB Connected
(Bus-Powered) ................................................................................................... 35
Figure 4.4. Connection Diagram with Voltage Regulator Used and USB Connected
(Self-Powered) ................................................................................................... 35
Figure 4.5. Connection Diagram for USB Pins ........................................................ 36
Figure 4.6. Connection Diagram for Internal Voltage Reference ............................. 36
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 46
Figure 6.2. Typical Temperature Sensor Transfer Function .................................... 48
Figure 6.3. Temperature Sensor Error with 1-Point Calibration .............................. 49
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing ............................. 51
Figure 6.5. ADC0 Equivalent Input Circuits ............................................................. 52
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 58
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 58
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 62
Figure 8.1. Comparator0 Functional Block Diagram ............................................... 64
Figure 8.2. Comparator1 Functional Block Diagram ............................................... 65
Figure 8.3. Comparator Hysteresis Plot .................................................................. 66
Figure 8.4. Comparator Input Multiplexer Block Diagram ........................................ 71
Figure 11.1. CIP-51 Block Diagram ......................................................................... 79
Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F380/1/4/5) ............. 89
Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F382/3/6/7) ............. 90
Figure 13.3. On-Chip Memory Map for 16 kB Devices (C8051F38C) ..................... 91
Figure 14.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ ... 94
Figure 14.2. Multiplexed Configuration Example ..................................................... 98
Figure 14.3. Non-multiplexed Configuration Example ............................................. 99
Figure 14.4. EMIF Operating Modes ..................................................................... 100
Figure 14.5. Non-Multiplexed 16-bit MOVX Timing ............................................... 104
Figure 14.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 105
Figure 14.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 106
Figure 14.8. Multiplexed 16-bit MOVX Timing ....................................................... 107
C8051F380/1/2/3/4/5/6/7/C
9 Rev. 1.5
Figure 14.9. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 108
Figure 14.10. Multiplexed 8-bit MOVX with Bank Select Timing ........................... 109
Figure 17.1. Reset Sources ................................................................................... 129
Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 130
Figure 18.1. Flash Program Memory Map and Security Byte ................................ 137
Figure 19.1. Oscillator Options .............................................................................. 142
Figure 19.2. External Crystal Example .................................................................. 150
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 153
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 154
Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 155
Figure 20.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped) ............................................................................................ 156
Figure 20.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)
............................................................................................................. 157
Figure 21.1. USB0 Block Diagram ......................................................................... 172
Figure 21.2. USB0 Register Access Scheme ........................................................ 175
Figure 21.3. USB FIFO Allocation ......................................................................... 181
Figure 22.1. SMBus Block Diagram ...................................................................... 205
Figure 22.2. Typical SMBus Configuration ............................................................ 206
Figure 22.3. SMBus Transaction ........................................................................... 207
Figure 22.4. Typical SMBus SCL Generation ........................................................ 209
Figure 22.5. Typical Master Write Sequence ........................................................ 223
Figure 22.6. Typical Master Read Sequence ........................................................ 224
Figure 22.7. Typical Slave Write Sequence .......................................................... 225
Figure 22.8. Typical Slave Read Sequence .......................................................... 226
Figure 23.1. UART0 Block Diagram ...................................................................... 232
Figure 23.2. UART0 Baud Rate Logic ................................................................... 233
Figure 23.3. UART Interconnect Diagram ............................................................. 234
Figure 23.4. 8-Bit UART Timing Diagram .............................................................. 234
Figure 23.5. 9-Bit UART Timing Diagram .............................................................. 235
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 236
Figure 24.1. UART1 Block Diagram ...................................................................... 240
Figure 24.2. UART1 Timing Without Parity or Extra Bit ......................................... 242
Figure 24.3. UART1 Timing With Parity ................................................................ 242
Figure 24.4. UART1 Timing With Extra Bit ............................................................ 242
Figure 24.5. Typical UART Interconnect Diagram ................................................. 243
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 244
Figure 25.1. SPI Block Diagram ............................................................................ 250
Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 252
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
............................................................................................................. 252
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
............................................................................................................. 253
Figure 25.5. Master Mode Data/Clock Timing ....................................................... 255
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 255
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 10
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 256
Figure 25.8. SPI Master Timing (CKPHA = 0) ....................................................... 260
Figure 25.9. SPI Master Timing (CKPHA = 1) ....................................................... 260
Figure 25.10. SPI Slave Timing (CKPHA = 0) ....................................................... 261
Figure 25.11. SPI Slave Timing (CKPHA = 1) ....................................................... 261
Figure 26.1. T0 Mode 0 Block Diagram ................................................................. 267
Figure 26.2. T0 Mode 2 Block Diagram ................................................................. 268
Figure 26.3. T0 Mode 3 Block Diagram ................................................................. 269
Figure 26.4. Timer 2 16-Bit Mode Block Diagram ................................................. 274
Figure 26.5. Timer 2 8-Bit Mode Block Diagram ................................................... 275
Figure 26.6. Timer 2 Capture Mode (T2SPLIT = 0) ............................................... 276
Figure 26.7. Timer 2 Capture Mode (T2SPLIT = 0) ............................................... 277
Figure 26.8. Timer 3 16-Bit Mode Block Diagram ................................................. 281
Figure 26.9. Timer 3 8-Bit Mode Block Diagram ................................................... 282
Figure 26.10. Timer 3 Capture Mode (T3SPLIT = 0) ............................................. 283
Figure 26.11. Timer 3 Capture Mode (T3SPLIT = 0) ............................................. 284
Figure 26.12. Timer 4 16-Bit Mode Block Diagram ............................................... 288
Figure 26.13. Timer 4 8-Bit Mode Block Diagram ................................................. 289
Figure 26.14. Timer 5 16-Bit Mode Block Diagram ............................................... 293
Figure 26.15. Timer 5 8-Bit Mode Block Diagram ................................................. 294
Figure 27.1. PCA Block Diagram ........................................................................... 298
Figure 27.2. PCA Counter/Timer Block Diagram ................................................... 299
Figure 27.3. PCA Interrupt Block Diagram ............................................................ 300
Figure 27.4. PCA Capture Mode Diagram ............................................................. 302
Figure 27.5. PCA Software Timer Mode Diagram ................................................. 303
Figure 27.6. PCA High-Speed Output Mode Diagram ........................................... 304
Figure 27.7. PCA Frequency Output Mode ........................................................... 305
Figure 27.8. PCA 8-Bit PWM Mode Diagram ........................................................ 306
Figure 27.9. PCA 16-Bit PWM Mode ..................................................................... 307
Figure 27.10. PCA Module 4 with Watchdog Timer Enabled ................................ 308
Figure 28.1. Typical C2 Pin Sharing ...................................................................... 319
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 11
List of Tables
Table 1.1. Product Selection Guide ......................................................................... 17
Table 2.1. C8051F38x Replacement Part Numbers ................................................ 20
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C ................................. 22
Table 3.2. TQFP-48 Package Dimensions .............................................................. 26
Table 3.3. TQFP-48 PCB Land Pattern Dimensions ............................................... 27
Table 3.4. LQFP-32 Package Dimensions .............................................................. 29
Table 3.5. LQFP-32 PCB Land Pattern Dimensions ............................................... 30
Table 3.6. QFN-32 Package Dimensions ................................................................ 32
Table 3.7. QFN-32 PCB Land Pattern Dimensions ................................................. 33
Table 5.1. Absolute Maximum Ratings .................................................................... 37
Table 5.2. Global Electrical Characteristics ............................................................. 38
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 39
Table 5.4. Reset Electrical Characteristics .............................................................. 39
Table 5.5. Internal Voltage Regulator Electrical Characteristics ............................. 40
Table 5.6. Flash Electrical Characteristics .............................................................. 40
Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 41
Table 5.8. Internal Low-Frequency Oscillator Electrical Characteristics ................. 41
Table 5.9. External Oscillator Electrical Characteristics .......................................... 41
Table 5.10. ADC0 Electrical Characteristics ............................................................ 42
Table 5.11. Temperature Sensor Electrical Characteristics .................................... 43
Table 5.12. Voltage Reference Electrical Characteristics ....................................... 43
Table 5.13. Comparator Electrical Characteristics .................................................. 44
Table 5.14. USB Transceiver Electrical Characteristics .......................................... 45
Table 11.1. CIP-51 Instruction Set Summary .......................................................... 81
Table 14.1. AC Parameters for External Memory Interface ................................... 110
Table 15.1. Special Function Register (SFR) Memory Map .................................. 112
Table 15.2. Special Function Registers ................................................................. 113
Table 16.1. Interrupt Summary .............................................................................. 120
Table 21.1. Endpoint Addressing Scheme ............................................................ 173
Table 21.2. USB0 Controller Registers ................................................................. 178
Table 21.3. FIFO Configurations ........................................................................... 182
Table 22.1. SMBus Clock Source Selection .......................................................... 209
Table 22.2. Minimum SDA Setup and Hold Times ................................................ 210
Table 22.3. Sources for Hardware Changes to SMBnCN ..................................... 217
Table 22.4. Hardware Address Recognition Examples (EHACK = 1) ................... 218
Table 22.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) ...... 227
Table 22.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) ...... 229
Table 23.1. Timer Settings for Standard Baud Rates Using Internal Oscillator ..... 238
Table 24.1. Baud Rate Generator Settings for Standard Baud Rates ................... 241
Table 25.1. SPI Slave Timing Parameters ............................................................ 262
Table 27.1. PCA Timebase Input Options ............................................................. 299
Table 27.2. PCA0CPM Bit Settings for PCA Capture/Compare Modules ............. 301
Table 27.3. Watchdog Timer Timeout Intervals1 ................................................... 310
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 12
List of Registers
SFR Definition 6.1. ADC0CF: ADC0 Configuration ...................................................... 53
SFR Definition 6.2. ADC0H: ADC0 Data Word MSB .................................................... 54
SFR Definition 6.3. ADC0L: ADC0 Data Word LSB ...................................................... 54
SFR Definition 6.4. ADC0CN: ADC0 Control ................................................................ 55
SFR Definition 6.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 56
SFR Definition 6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 56
SFR Definition 6.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 57
SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 57
SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select ..................................... 60
SFR Definition 6.10. AMX0N: AMUX0 Negative Channel Select ................................. 61
SFR Definition 7.1. REF0CN: Reference Control ......................................................... 63
SFR Definition 8.1. CPT0CN: Comparator0 Control ..................................................... 67
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection ....................................... 68
SFR Definition 8.3. CPT1CN: Comparator1 Control ..................................................... 69
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection ....................................... 70
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection ........................................ 72
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection ........................................ 73
SFR Definition 9.1. REG01CN: Voltage Regulator Control .......................................... 75
SFR Definition 10.1. PCON: Power Control .................................................................. 78
SFR Definition 11.1. DPL: Data Pointer Low Byte ........................................................ 85
SFR Definition 11.2. DPH: Data Pointer High Byte ....................................................... 85
SFR Definition 11.3. SP: Stack Pointer ......................................................................... 86
SFR Definition 11.4. ACC: Accumulator ....................................................................... 86
SFR Definition 11.5. B: B Register ................................................................................ 86
SFR Definition 11.6. PSW: Program Status Word ........................................................ 87
SFR Definition 12.1. PFE0CN: Prefetch Engine Control .............................................. 88
SFR Definition 14.1. EMI0CN: External Memory Interface Control .............................. 96
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration ..................... 97
SFR Definition 14.3. EMI0TC: External Memory TIming Control ................................ 103
SFR Definition 15.1. SFRPAGE: SFR Page ............................................................... 111
SFR Definition 16.1. IE: Interrupt Enable .................................................................... 121
SFR Definition 16.2. IP: Interrupt Priority .................................................................... 122
SFR Definition 16.3. EIE1: Extended Interrupt Enable 1 ............................................ 123
SFR Definition 16.4. EIP1: Extended Interrupt Priority 1 ............................................ 124
SFR Definition 16.5. EIE2: Extended Interrupt Enable 2 ............................................ 125
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2 ............................................ 126
SFR Definition 16.7. IT01CF: INT0/INT1 ConfigurationO ........................................... 128
SFR Definition 17.1. VDM0CN: VDD Monitor Control ................................................ 132
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 134
SFR Definition 18.1. PSCTL: Program Sto
re R/W Control ......................................... 139
SFR Definition 18.2. FLKEY: Flash Lock and Key ...................................................... 140
SFR Definition 18.3. FLSCL: Flash Scale ................................................................... 141
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 144
C8051F380/1/2/3/4/5/6/7/C
13 Rev. 1.5
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration .............................. 145
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control ................................... 146
SFR Definition 19.4. CLKMUL: Clock Multiplier Control ............................................. 147
SFR Definition 19.5. OSCLCN: Internal L-F Oscillator Control ................................... 148
SFR Definition 19.6. OSCXCN: External Oscillator Control ........................................ 152
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 .......................................... 159
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 .......................................... 160
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2 .......................................... 161
SFR Definition 20.4. P0: Port 0 ................................................................................... 162
SFR Definition 20.5. P0MDIN: Port 0 Input Mode ....................................................... 162
SFR Definition 20.6. P0MDOUT: Port 0 Output Mode ................................................ 163
SFR Definition 20.7. P0SKIP: Port 0 Skip ................................................................... 163
SFR Definition 20.8. P1: Port 1 ................................................................................... 164
SFR Definition 20.9. P1MDIN: Port 1 Input Mode ....................................................... 164
SFR Definition 20.10. P1MDOUT: Port 1 Output Mode .............................................. 165
SFR Definition 20.11. P1SKIP: Port 1 Skip ................................................................. 165
SFR Definition 20.12. P2: Port 2 ................................................................................. 166
SFR Definition 20.13. P2MDIN: Port 2 Input Mode ..................................................... 166
SFR Definition 20.14. P2MDOUT: Port 2 Output Mode .............................................. 167
SFR Definition 20.15. P2SKIP: Port 2 Skip ................................................................. 167
SFR Definition 20.16. P3: Port 3 ................................................................................. 168
SFR Definition 20.17. P3MDIN: Port 3 Input Mode ..................................................... 168
SFR Definition 20.18. P3MDOUT: Port 3 Output Mode .............................................. 169
SFR Definition 20.19. P3SKIP: Port 3 Skip ................................................................. 169
SFR Definition 20.20. P4: Port 4 ................................................................................. 170
SFR Definition 20.21. P4MDIN: Port 4 Input Mode ..................................................... 170
SFR Definition 20.22. P4MDOUT: Port 4 Output Mode .............................................. 171
SFR Definition 21.1. USB0XCN: USB0 Transceiver Control ...................................... 174
SFR Definition 21.2. USB0ADR: USB0 Indirect Address ........................................... 176
SFR Definition 21.3. USB0DAT: USB0 Data .............................................................. 177
USB Register Definition 21.4. INDEX: USB0 Endpoint Index ..................................... 179
USB Register Definition 21.5. CLKREC: Clock Recovery Control .............................. 180
USB Register Definition 21.6. FIFOn: USB0 Endpoint FIFO Access .......................... 182
USB Register Definition 21.7. FADDR: USB0 Function Address ............................... 183
USB Register Definition 21.8. POWER: USB0 Power ................................................ 185
USB Register Definition 21.9. FRAMEL: USB0 Frame Number Low ......................... 186
USB Register Definition 21.10. FRAMEH: USB0 Frame Number High ...................... 186
USB Register Definition 21.11. IN1INT: USB0 IN Endpoint Interrupt ......................... 187
USB Register Definition 21.12. OUT1INT: USB0 OUT Endpoint Interrupt ................. 188
USB Register Definition 21.13. CMINT: USB0 Common Interr
upt ............................. 189
USB Register Definition 21.14. IN1IE: USB0 IN Endpoint Interrupt Enable ............... 190
USB Register Definition 21.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable ....... 191
USB Register Definition 21.16. CMIE: USB0 Common Interrupt Enable .................... 192
USB Register Definition 21.17. E0CSR: USB0 Endpoint0 Control ............................. 195
USB Register Definition 21.18. E0CNT: USB0 Endpoint0 Data Count ....................... 196
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 14
USB Register Definition 21.19. EENABLE: USB0 Endpoint Enable ........................... 197
USB Register Definition 21.20. EINCSRL: USB0 IN Endpoint Control Low ............... 199
USB Register Definition 21.21. EINCSRH: USB0 IN Endpoint Control High .............. 200
USB Register Definition 21.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 202
USB Register Definition 21.23. EOUTCSRH: USB0 OUT Endpoint Control High Byte ....
203
USB Register Definition 21.24. EOUTCNTL: USB0 OUT Endpoint Count Low ......... 203
USB Register Definition 21.25. EOUTCNTH: USB0 OUT Endpoint Count High ........ 204
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration ...................................... 211
SFR Definition 22.2. SMB1CF: SMBus Clock/Configuration ...................................... 212
SFR Definition 22.3. SMBTC: SMBus Timing Control ................................................ 213
SFR Definition 22.4. SMB0CN: SMBus Control .......................................................... 215
SFR Definition 22.5. SMB1CN: SMBus Control .......................................................... 216
SFR Definition 22.6. SMB0ADR: SMBus0 Slave Address .......................................... 218
SFR Definition 22.7. SMB0ADM: SMBus0 Slave Address Mask ................................ 219
SFR Definition 22.8. SMB1ADR: SMBus1 Slave Address .......................................... 219
SFR Definition 22.9. SMB1ADM: SMBus1 Slave Address Mask ................................ 220
SFR Definition 22.10. SMB0DAT: SMBus Data .......................................................... 221
SFR Definition 22.11. SMB1DAT: SMBus Data .......................................................... 222
SFR Definition 23.1. SCON0: Serial Port 0 Control .................................................... 237
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 238
SFR Definition 24.1. SCON1: UART1 Control ............................................................ 245
SFR Definition 24.2. SMOD1: UART1 Mode .............................................................. 246
SFR Definition 24.3. SBUF1: UART1 Data Buffer ...................................................... 247
SFR Definition 24.4. SBCON1: UART1 Baud Rate Generator Control ...................... 248
SFR Definition 24.5. SBRLH1: UART1 Baud Rate Generator High Byte ................... 248
SFR Definition 24.6. SBRLL1: UART1 Baud Rate Generator Low Byte ..................... 249
SFR Definition 25.1. SPI0CFG: SPI0 Configuration ................................................... 257
SFR Definition 25.2. SPI0CN: SPI0 Control ............................................................... 258
SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate ....................................................... 259
SFR Definition 25.4. SPI0DAT: SPI0 Data ................................................................. 259
SFR Definition 26.1. CKCON: Clock Control .............................................................. 264
SFR Definition 26.2. CKCON1: Clock Control 1 ......................................................... 265
SFR Definition 26.3. TCON: Timer Control ................................................................. 270
SFR Definition 26.4. TMOD: Timer Mode ................................................................... 271
SFR Definition 26.5. TL0: Timer 0 Low Byte ............................................................... 272
SFR Definition 26.6. TL1: Timer 1 Low Byte ............................................................... 272
SFR Definition 26.7. TH0: Timer 0 High Byte ............................................................. 273
SFR Definition 26.8. TH1: Timer 1 High Byte ............................................................. 273
SFR Definition 26.9. TMR2CN: Timer 2 Control ......................................................... 278
SFR Definition 26.10. TMR2RLL: Timer 2 Reload Register Low Byte ........................ 279
SFR Definition 26.11. TMR2RLH: Timer 2 Reload Register High Byte ...................... 279
SFR Definition 26.12. TMR2L: Timer 2 Low Byte ....................................................... 279
SFR Definition 26.13. TMR2H Timer 2 High Byte ....................................................... 280
SFR Definition 26.14. TMR3CN: Timer 3 Control ....................................................... 285
C8051F380/1/2/3/4/5/6/7/C
15 Rev. 1.5
SFR Definition 26.15. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 286
SFR Definition 26.16. TMR3RLH: Timer 3 Reload Register High Byte ...................... 286
SFR Definition 26.17. TMR3L: Timer 3 Low Byte ....................................................... 286
SFR Definition 26.18. TMR3H Timer 3 High Byte ....................................................... 287
SFR Definition 26.19. TMR4CN: Timer 4 Control ....................................................... 290
SFR Definition 26.20. TMR4RLL: Timer 4 Reload Register Low Byte ........................ 291
SFR Definition 26.21. TMR4RLH: Timer 4 Reload Register High Byte ...................... 291
SFR Definition 26.22. TMR4L: Timer 4 Low Byte ....................................................... 291
SFR Definition 26.23. TMR4H Timer 4 High Byte ....................................................... 292
SFR Definition 26.24. TMR5CN: Timer 5 Control ....................................................... 295
SFR Definition 26.25. TMR5RLL: Timer 5 Reload Register Low Byte ........................ 296
SFR Definition 26.26. TMR5RLH: Timer 5 Reload Register High Byte ...................... 296
SFR Definition 26.27. TMR5L: Timer 5 Low Byte ....................................................... 296
SFR Definition 26.28. TMR5H Timer 5 High Byte ....................................................... 297
SFR Definition 27.1. PCA0CN: PCA Control .............................................................. 311
SFR Definition 27.2. PCA0MD: PCA Mode ................................................................ 312
SFR Definition 27.3. PCA0CPMn: PCA Capture/Compare Mode .............................. 313
SFR Definition 27.4. PCA0L: PCA Counter/Timer Low Byte ...................................... 314
SFR Definition 27.5. PCA0H: PCA Counter/Timer High Byte ..................................... 314
SFR Definition 27.6. PCA0CPLn: PCA Capture Module Low Byte ............................. 315
SFR Definition 27.7. PCA0CPHn: PCA Capture Module High Byte ........................... 315
C2 Register Definition 28.1. C2ADD: C2 Address ...................................................... 316
C2 Register Definition 28.2. DEVICEID: C2 Device ID ............................................... 317
C2 Register Definition 28.3. REVID: C2 Revision ID .................................................. 317
C2 Register Definition 28.4. FPCTL: C2 Flash Programming Control ........................ 318
C2 Register Definition 28.5. FPDAT: C2 Flash Programming Data ............................ 318
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 19
1. System Overview
C8051F380/1/2/3/4/5/6/7/C devices are fully integrated mixed-signal System-on-a-Chip MCUs. High-
lighted features are listed below. Refer to Table 1.1 for specific product feature selection.
High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated
transceiver, and 1 kB FIFO RAM
Supply Voltage Regulator
True 10-bit 500 ksps differential / single-ended ADC with analog multiplexer
On-chip Voltage Reference and Temperature Sensor
On-chip Voltage Comparators (2)
Precision internal calibrated 48 MHz internal oscillator
Internal low-frequency oscillator for additional power savings
Up to 64 kB of on-chip Flash memory
Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
External Memory Interface (EMIF) available on 48-pin versions.
2 I
2
C/SMBus, 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, V
DD
Monitor, and Missing Clock Detector
Up to 40 Port I/O (5 V tolerant)
With on-chip Power-On Reset, V
DD
monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F380/1/2/3/4/5/6/7/C devices are truly stand-alone System-on-a-Chip solutions. The Flash memory
can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
For voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3.0 V is required for
USB communication. The Port I/O and RST
pins are tolerant of input signals up to 5 V. C8051F380/1/2/3/
4/5/6/7/C devices are available in 48-pin TQFP, 32-pin LQFP, or 32-pin QFN packages. See Table 1.1,
“Product Selection Guide,” on page 20 for feature and package choices.
C8051F380/1/2/3/4/5/6/7/C
20 Rev. 1.5
Table 1.1. Product Selection Guide
Ordering Part Number
MIPS (Peak)
Flash Memory (Bytes)
RAM
Calibrated Internal Oscillator
Low Frequency Oscillator
USB with 1k Endpoint RAM
Supply Voltage Regulator
SMBus/I2C
Enhanced SPI
UARTs
Timers (16-bit)
Programmable Counter Array
Digital Port I/O
External Memory Interface (EMIF)
10-bit 500ksps ADC
Temperature Sensor
Voltage Reference
Analog Comparators
Package
C8051F380-GQ
48 64k 4352 2 26 40 2TQFP48
C8051F381-GQ
48 64k 4352
2
26
25 —
2LQFP32
C8051F381-GM
48 64k 4352 2 26 25 — 2QFN32
C8051F382-GQ
48 32k 2304 2 26 40 2TQFP48
C8051F383-GQ
48 32k 2304 2 26 25 — 2LQFP32
C8051F383-GM
48 32k 2304
2
26
25 —
2QFN32
C8051F384-GQ
48 64k 4352 2 26 40 ———2 TQFP48
C8051F385-GQ
48 64k 4352 2 26 25 ————2 LQFP32
C8051F385-GM
48 64k 4352 2 26 25 ————2 QFN32
C8051F386-GQ
48 32k 2304
2
26
40
———2 TQFP48
C8051F387-GQ
48 32k 2304 2 26 2
5 —
———2 LQFP32
C8051F387-GM
48 32k 2304 2 26 25 ————2 QFN32
C8051F38C-GQ
48 16k 2304 2 26 25 — 2LQFP32
C8051F38C-GM
48 16k 2304
2
26
25 —
2QFN32
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 21
Figure 1.1. C8051F380/2/4/6 Block Diagram
Analog Peripherals
10-bit
500ksps
ADC
A
M
U
X
Temp
Sensor
2 Comparators
+
-
VREFVDD
CP0
VDD
+
-
CP1
VREF
Debug / Programming
Hardware
Port 0
Drivers
P0.0
AIN0 - AIN19
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3, 4, 5
PCA/WDT
SMBus1
UART1
SPI
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL1
P0.7/XTAL2
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4/CNVSTR
P1.5/VREF
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Supply
Monitor
System Clock Setup
External Oscillator
Internal Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator
Clock
Recovery
USB Peripheral
Controller
1k Byte
RAM
Full / Low
Speed
Transceiver
External Memory
Interface
Control
Address
Data
P1
P2 / P3
P4
SFR
Bus
Voltage
Regulators
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
C2D
CIP-51 8051
Controller Core
64/32k Byte ISP FLASH
Program Memory
256 Byte RAM
4/2k Byte XRAM
SMBus0
C8051F380/1/2/3/4/5/6/7/C
22 Rev. 1.5
Figure 1.2. C8051F381/3/5/7/C Block Diagram
Analog Peripherals
10-bit
500 ksps
ADC
A
M
U
X
Temp
Sensor
2 Comparators
+
-
VREFVDD
CP0
VDD
+
-
CP1
VREF
Debug / Programming
Hardware
Port 0
Drivers
P0.0
AIN0 - AIN20
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3, 4, 5
PCA/WDT
SPI
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Supply
Monitor
System Clock Setup
External Oscillator
Internal Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator
Clock
Recovery
USB Peripheral
Controller
1 kB RAM
Full / Low
Speed
Transceiver
SFR
Bus
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
CIP-51 8051
Controller Core
64/32/16 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
C2D
SMBus1
SMBus0
Voltage
Regulators
UART1
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 23
2. C8051F34x Compatibility
The C8051F38x family is designed to be a pin and code compatible replacement for the C8051F34x
device family, with an enhanced feature set. The C8051F38x device should function as a drop-in replace-
ment for the C8051F34x devices in most applications. Table 2.1 lists recommended replacement part
numbers for C8051F34x devices. See “2.1. Hardware Incompatibilities” to determine if any changes are
necessary when upgrading an existing C8051F34x design to the C8051F38x.
Table 2.1. C8051F38x Replacement Part Numbers
C8051F34x Part Number C8051F38x Part Number
C8051F340-GQ C8051F380-GQ
C8051F341-GQ C8051F382-GQ
C8051F342-GQ C8051F381-GQ
C8051F342-GM C8051F381-GM
C8051F343-GQ C8051F383-GQ
C8051F343-GM C8051F383-GM
C8051F344-GQ C8051F380-GQ
C8051F345-GQ C8051F382-GQ
C8051F346-GQ C8051F381-GQ
C8051F346-GM C8051F381-GM
C8051F347-GQ C8051F383-GQ
C8051F347-GM C8051F383-GM
C8051F348-GQ C8051F386-GQ
C8051F349-GQ C8051F387-GQ
C8051F349-GM C8051F387-GM
C8051F34A-GQ C8051F381-GQ
C8051F34A-GM C8051F381-GM
C8051F34B-GQ C8051F383-GQ
C8051F34B-GM C8051F383-GM
C8051F34C-GQ C8051F384-GQ
C8051F34D-GQ C8051F385-GQ
C8051F380/1/2/3/4/5/6/7/C
24 Rev. 1.5
2.1. Hardware Incompatibilities
While the C8051F38x family includes a number of new features not found on the C8051F34x family, there
are some differences that should be considered for any design port.
Clock Multiplier: The C8051F38x does not include the 4x clock multiplier from the C8051F34x device
families. This change only impacts systems which use the clock multiplier in conjunction with an
external oscillator source.
External Oscillator C and RC Modes: The C and RC modes of the oscillator have a divide-by-2 stage
on the C8051F38x to aid in noise immunity. This was not present on the C8051F34x device family, and
any clock generated with C or RC mode will change accordingly.
Fab Technology: The C8051F38x is manufactured using a different technology process than the
C8051F34x. As a result, many of the electrical performance parameters will have subtle differences.
These differences should not affect most systems but it is nonetheless important to review the electrical
parameters for any blocks that are used in the design, and ensure they are compatible with the existing
hardware.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 25
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C
Name Pin Numbers Type Description
48-pin 32-pin
V
DD
10 6 Power In
Power
Out
2.7–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output.
GND 7 3 Ground.
RST
/
C2CK
13 9 D I/O
D I/O
Device Reset. Open-drain output of internal POR or V
DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs.
Clock signal for the C2 Debug Interface.
C2D 14 — D I/O Bi-directional data signal for the C2 Debug Interface.
P3.0 /
C2D
— 10 D I/O
D I/O
Port 3.0. See Section 20 for a complete description of Port 3.
Bi-directional data signal for the C2 Debug Interface.
REGIN 11 7 Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
age regulator.
VBUS 12 8 D In VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin indi-
cates a USB network connection.
D+ 8 4 D I/O USB D+.
D– 9 5 D I/O USB D–.
P0.0 6 2 D I/O or
A In
Port 0.0. See Section 20 for a complete description of Port 0.
P0.1 5 1 D I/O or
A In
Port 0.1.
P0.2 4 32 D I/O or
A In
Port 0.2.
P0.3 3 31 D I/O or
A In
Port 0.3.
P0.4 2 30 D I/O or
A In
Port 0.4.
P0.5 1 29 D I/O or
A In
Port 0.5.
P0.6 48 28 D I/O or
A In
Port 0.6.
C8051F380/1/2/3/4/5/6/7/C
26 Rev. 1.5
P0.7 47 27 D I/O or
A In
Port 0.7.
P1.0 46 26 D I/O or
A In
Port 1.0. See Section 20 for a complete description of Port 1.
P1.1 45 25 D I/O or
A In
Port 1.1.
P1.2 44 24 D I/O or
A In
Port 1.2.
P1.3 43 23 D I/O or
A In
Port 1.3.
P1.4 42 22 D I/O or
A In
Port 1.4.
P1.5 41 21 D I/O or
A In
Port 1.5.
P1.6 40 20 D I/O or
A In
Port 1.6.
P1.7 39 19 D I/O or
A In
Port 1.7.
P2.0 38 18 D I/O or
A In
Port 2.0. See Section 20 for a complete description of Port 2.
P2.1 37 17 D I/O or
A In
Port 2.1.
P2.2 36 16 D I/O or
A In
Port 2.2.
P2.3 35 15 D I/O or
A In
Port 2.3.
P2.4 34 14 D I/O or
A In
Port 2.4.
P2.5 33 13 D I/O or
A In
Port 2.5.
P2.6 32 12 D I/O or
A In
Port 2.6.
P2.7 31 11 D I/O or
A In
Port 2.7.
P3.0 30 — D I/O or
A In
Port 3.0. See Section 20 for a complete description of Port 3.
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C (Continued)
Name Pin Numbers Type Description
48-pin 32-pin
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 27
P3.1 29 — D I/O or
A In
Port 3.1.
P3.2 28 — D I/O or
A In
Port 3.2.
P3.3 27 — D I/O or
A In
Port 3.3.
P3.4 26 — D I/O or
A In
Port 3.4.
P3.5 25 — D I/O or
A In
Port 3.5.
P3.6 24 — D I/O or
A In
Port 3.6.
P3.7 23 — D I/O or
A In
Port 3.7.
P4.0 22 — D I/O or
A In
Port 4.0. See Section 20 for a complete description of Port 4.
P4.1 21 — D I/O or
A In
Port 4.1.
P4.2 20 — D I/O or
A In
Port 4.2.
P4.3 19 — D I/O or
A In
Port 4.3.
P4.4 18 — D I/O or
A In
Port 4.4.
P4.5 17 — D I/O or
A In
Port 4.5.
P4.6 16 — D I/O or
A In
Port 4.6.
P4.7 15 — D I/O or
A In
Port 4.7.
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C (Continued)
Name Pin Numbers Type Description
48-pin 32-pin
C8051F380/1/2/3/4/5/6/7/C
28 Rev. 1.5
Figure 3.1. TQFP-48 Pinout Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
VBUS
P2.2
P2.0
P1.7
P1.6
P1.2
P2.4
P2.3
P3.5
P3.4
P3.2
P3.1
P2.1
P0.6
P3.3
P0.7
P0.2
D-
REGIN
P0.3
P3.0
P1.4
P1.5
P0.5
P1.1
P1.0
P0.4
P1.3
13
14
15
16
17
18
19
20
21
22
23
24
P2.6
P2.5
C8051F380/2/4/6-GQ
Top View
GND
D+
P0.1
P0.0
VDD
P2.7
P3.6
P4.1
P4.0
P3.7
P4.2
P4.5
P4.4
P4.3
P4.6
RST / C2CK
C2D
P4.7
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 29
Figure 3.2. TQFP-48 Package Diagram
Table 3.2. TQFP-48 Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A — — 1.20 E 9.00 BSC
A1 0.05 — 0.15 E1 7.00 BSC
A2 0.95 1.00 1.05 L 0.45 0.60 0.75
b 0.17 0.22 0.27 aaa 0.20
c 0.09 — 0.20 bbb 0.20
D 9.00 BSC ccc 0.08
D1 7.00 BSC ddd 0.08
e 0.50 BSC q 0° 3.5° 7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation ABC.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F380/1/2/3/4/5/6/7/C
30 Rev. 1.5
Figure 3.3. TQFP-48 Recommended PCB Land Pattern
Table 3.3. TQFP-48 PCB Land Pattern Dimensions
Dimension Min Max
C1 8.30 8.40
C2 8.30 8.40
E0.50 BSC
X1 0.20 0.30
Y1 1.40 1.50
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 31
Figure 3.4. LQFP-32 Pinout Diagram (Top View)
1
VBUS
P1.2
P1.7
P1.4
P1.3
P1.5D+
D–
GND
P0.1
P0.0
P2.0
P2.1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
P1.6
C8051F381/3/5/7/C-GQ
Top View
VDD
REGIN
RST / C2CK
P3.0 / C2D
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P1.1
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
C8051F380/1/2/3/4/5/6/7/C
32 Rev. 1.5
Figure 3.5. LQFP-32 Package Diagram
Table 3.4. LQFP-32 Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A — — 1.60 E 9.00 BSC
A1 0.05 — 0.15 E1 7.00 BSC
A2 1.35 1.40 1.45 L 0.45 0.60 0.75
b 0.300.370.45 aaa 0.20
c 0.09 — 0.20 bbb 0.20
D 9.00 BSC ccc 0.10
D1 7.00 BSC ddd 0.20
e 0.80 BSC q 0°3.5°7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 33
Figure 3.6. LQFP-32 Recommended PCB Land Pattern
Table 3.5. LQFP-32 PCB Land Pattern Dimensions
Dimension Min Max
C1 8.40 8.50
C2 8.40 8.50
E0.80 BSC
X1 0.40 0.50
Y1 1.25 1.35
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
C8051F380/1/2/3/4/5/6/7/C
34 Rev. 1.5
Figure 3.7. QFN-32 Pinout Diagram (Top View)
25 P1.1
17 P2.1
16P2.2
8VBUS
32
31
30
29
28
27
26
1
2
3
4
5
6
7
9
10
11
12
13
14
15
24
23
22
21
20
19
18
GND (optional)
C8051F381/3/5/7/C-GM
Top View
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
GND
D+
D–
VDD
REGIN
RST / C2CK
P3.0 / C2D
P2.7
P2.6
P2.5
P2.4
P2.3
P2.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 35
Figure 3.8. QFN-32 Package Drawing
Table 3.6. QFN-32 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 0.80 0.85 0.90 E2 3.20 3.30 3.40
A1 0.00 0.02 0.05 L 0.35 0.40 0.45
b 0.18 0.25 0.30 aaa — — 0.10
D 5.00 BSC bbb — — 0.10
D2 3.20 3.30 3.40 ddd — — 0.05
e 0.50 BSC eee — — 0.08
E 5.00 BSC
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
C8051F380/1/2/3/4/5/6/7/C
36 Rev. 1.5
Figure 3.9. QFN-32 Recommended PCB Land Pattern
Table 3.7. QFN-32 PCB Land Pattern Dimensions
Dimension Min Max Dimension Min Max
C1 4.80 4.90 X2 3.20 3.40
C2 4.80 4.90 Y1 0.75 0.85
E 0.50 BSC Y2 3.20 3.40
X1 0.20 0.30
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure
the proper paste volume.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 38
4. Typical Connection Diagrams
This section provides typical connection diagrams for C8051F38x devices.
4.1. Power
Figure 4.1 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator is in use and USB is not used.
Figure 4.1. Connection Diagram with Voltage Regulator Used and No USB
Figure 4.2 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator and USB are not used.
Figure 4.2. Connection Diagram with Voltage Regulator Not Used and No USB
Figure 4.3 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator used and USB is connected (bus-powered). The VBUS signal is used to detect when
C8051F38x Device
Voltage
Regulator
REGIN
GND
1 µF and 0.1 µF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
3.3 V (out)
3.6-5.25 V (in)
VDD
VBUS
C8051F38x Device
Voltage
Regulator
2.7-3.6 V (in)
GND
1 µF and 0.1 µF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
REGIN
VDD
VBUS
C8051F380/1/2/3/4/5/6/7/C
39 Rev. 1.5
USB is connected to a host device and is shown with a 100 Ω current-limiting resistor. This current-limiting
resistor is recommended for systems that may experience electrostatic discharge (ESD), latch-up, and
have a greater opportunity to share signals with systems that do not have the same ground potential. This
is not a required component for most applications.
Figure 4.3. Connection Diagram with Voltage Regulator Used and USB Connected
(Bus-Powered)
Figure 4.4 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator used and USB is connected (self-powered). The VBUS signal is used to detect when
USB is connected to a host device and is shown with a 100 Ω current-limiting resistor. This current-limiting
resistor is recommended for systems that may experience electrostatic discharge (ESD), latch-up, and
have a greater opportunity to share signals with systems that do not have the same ground potential. This
is not a required component for most applications.
Figure 4.4. Connection Diagram with Voltage Regulator Used and USB Connected
(Self-Powered)
Recommended,
not required
C8051F38x Device
Voltage
Regulator
REGIN
GND
1 μF and 0.1 μF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
3.3 V (out)
VBUS
USB 5 V (in)
VDD
100 ȍ
Recommended,
not required
C8051F38x Device
Voltage
Regulator
REGIN
GND
1 μF and 0.1 μF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
3.3 V (out)
VBUS
USB 5 V
(sense)
VDD
3.6-5.25 V (in)
100 ȍ
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 40
4.2. USB
Figure 4.5 shows a typical connection diagram for the USB pins of the C8051F38x devices including a
100 Ω current-limiting resistor on the VBUS sense pin and ESD protection diodes on the USB pins. This
current-limiting resistor is recommended for systems that may experience electrostatic discharge (ESD),
latch-up, and have a greater opportunity to share signals with systems that do not have the same ground
potential. This is not a required component for most applications.
Figure 4.5. Connection Diagram for USB Pins
4.3. Voltage Reference (VREF)
Figure 4.6 shows a typical connection diagram for the voltage reference (VREF) pin of the C8051F38x
devices when using the internal voltage reference. When using an external voltage reference, consult the
appropriate device’s data sheet for connection recommendations.
Figure 4.6. Connection Diagram for Internal Voltage Reference
C8051F38x Device
USB
D+
GND
VBUS
100 ȍ
D-
USB
Connector
Signal GND
VBUS
D+
D-
SP0503BAHT or
equivalent USB
ESD protection
diodes
Recommended,
not required
C8051F38x Device
Voltage
Reference
2.42 V (out)
GND
4.7 µF and 0.1 µF
capacitors recommended
for internal voltage
reference.
VREF
C8051F380/1/2/3/4/5/6/7/C
41 Rev. 1.5
5. Electrical Characteristics
5.1. Absolute Maximum Specifications
Table 5.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Junction Temperature Under Bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on RST
, VBUS, or any
Port I/O Pin with Respect to GND
V
DD
> 2.2 V
V
DD
< 2.2 V
–0.3
–0.3
—
—
5.8
V
DD
+ 3.6
V
V
Voltage on V
DD
with Respect to
GND
Regulator1 in Normal Mode
Regulator1 in Bypass Mode
–0.3
–0.3
—
—
4.2
1.98
V
V
Maximum Total Current through
V
DD
or GND
——500mA
Maximum Output Current sunk by
RST
or any Port Pin
——100mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 42
5.2. Electrical Characteristics
Table 5.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Digital Supply Voltage
1
V
RST
1
3.3 3.6 V
Digital Supply RAM Data
Retention Voltage
—1.5— V
SYSCLK (System Clock)
2
0—48MHz
Specified Operating
Temperature Range
–40 — +85 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
I
DD
3
SYSCLK = 48 MHz, V
DD
= 3.3 V — 12 14 mA
SYSCLK = 24 MHz, V
DD
= 3.3 V — 7 8 mA
SYSCLK = 1 MHz, V
DD
= 3.3 V — 0.45 0.85 mA
SYSCLK = 80 kHz, V
DD
= 3.3 V — 280 — µA
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle I
DD
3
SYSCLK = 48 MHz, V
DD
= 3.3 V — 6.5 8 mA
SYSCLK = 24 MHz, V
DD
= 3.3 V — 3.5 5 mA
SYSCLK = 1 MHz, V
DD
= 3.3 V — 0.35 — mA
SYSCLK = 80 kHz, V
DD
= 3.3 V — 220 — µA
Digital Supply Current
(Stop or Suspend Mode, shut-
down)
Oscillator not running (STOP mode),
Internal Regulators OFF, V
DD
= 3.3 V
—1—µA
Oscillator not running (STOP or SUS-
PEND mode), REG0 and REG1 both in
low power mode, V
DD
= 3.3 V.
—100— µA
Oscillator not running (STOP or SUS-
PEND mode), REG0 OFF, V
DD
= 3.3 V.
—150— µA
Digital Supply Current for USB
Module
(USB Active Mode
4
)
USB Clock = 48 MHz, V
DD
= 3.3 V — 8 — mA
Notes:
1. USB Requires 3.0 V Minimum Supply Voltage.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Includes normal mode bias current for REG0 and REG1. Does not include current from internal oscillators,
USB, or other analog peripherals.
4. An additional 220uA is sourced by the D+ or D- pull-up to the USB bus when the USB pull-up is active.
C8051F380/1/2/3/4/5/6/7/C
43 Rev. 1.5
Table 5.3. Port I/O DC Electrical Characteristics
V
DD
= 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Output High Voltage I
OH
= –3 mA, Port I/O push-pull
I
OH
= –10 µA, Port I/O push-pull
I
OH
= –10 mA, Port I/O push-pull
V
DD
–0.7
V
DD
–0.1
—
—
—
V
DD
–0.8
—
—
—
V
Output Low Voltage I
OL
= 8.5 mA
I
OL
= 10 µA
I
OL
= 25 mA
—
—
—
—
—
1.0
0.6
0.1
—
V
Input High Voltage 2.0 — — V
Input Low Voltage — — 0.8 V
Input Leakage
Current
Weak Pullup Off
Weak Pullup On, V
IN
= 0 V
—
—
—
15
±1
50
µA
Table 5.4. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
RST
Output Low Voltage
I
OL
= 8.5 mA,
V
DD
= 2.7 V to 3.6 V
——0.6V
RST
Input High Voltage 0.7 x V
DD
——V
RST
Input Low Voltage — — 0.3 x V
DD
V
RST
Input Pullup Current
RST
= 0.0 V
—1540µA
V
DD
Monitor Threshold (V
RST
) 2.60 2.65 2.70 V
Missing Clock Detector Time-
out
Time from last system clock
rising edge to reset initiation
80 580 800 µs
Reset Time Delay Delay between release of any
reset source and code
execution at location 0x0000
——250µs
Minimum RST
Low Time to
Generate a System Reset
15 — — µs
V
DD
Monitor Turn-on Time — — 100 µs
V
DD
Monitor Supply Current — 15 50 µA
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 44
Table 5.5. Internal Voltage Regulator Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Voltage Regulator (REG0)
Input Voltage Range
1
2.7 — 5.25 V
Output Voltage (V
DD
)
2
Output Current = 1 to 100 mA 3.0 3.3 3.6 V
Output Current
2
——100mA
Dropout Voltage (V
DO
)
3
—1—mV/mA
Voltage Regulator (REG1)
Input Voltage Range 1.8 — 3.6 V
Notes:
1. Input range specified for regulation. When an external regulator is used, should be tied to
V
DD
.
2. Output current is total regulator output, including any current required by the C8051F380/1/2/3/4/5/6/7/C.
3. The minimum input voltage is 2.70 V or V
DD
+ V
DO
(max load), whichever is greater.
Table 5.6. Flash Electrical Characteristics
Parameter Test Condition Min Typ Max Unit
Flash Size C8051F380/1/4/5*
C8051F382/3/6/7
65536*
32768
——Bytes
Bytes
Endurance 10k 100k — Erase/Write
Erase Cycle Time 25 MHz System Clock 10 15 22.5 ms
Write Cycle Time 25 MHz System Clock 10 15 20 µs
Notes:
1. 1024 bytes at location 0xFC00 to 0xFFFF are not available for program storage.
2. Data Retention Information is published in the Quarterly Quality and Reliability Report.
C8051F380/1/2/3/4/5/6/7/C
45 Rev. 1.5
Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics
V
DD
= 2.7 to 3.6 V; T
A
= –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Test Condition Min Typ Max Unit
Oscillator Frequency IFCN = 11b 47.3 48 48.7 MHz
Oscillator Supply Current
(from V
DD
)
25 °C, V
DD
= 3.0 V,
OSCICN.7 = 1,
OCSICN.5 = 0
— 900 — µA
Power Supply Sensitivity Constant Temperature — 110 — ppm/V
Temperature Sensitivity Constant Supply — 25 — ppm/°C
Table 5.8. Internal Low-Frequency Oscillator Electrical Characteristics
V
DD
= 2.7 to 3.6 V; T
A
= –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Test Condition Min Typ Max Unit
Oscillator Frequency OSCLD = 11b 75 80 85 kHz
Oscillator Supply Current
(from V
DD
)
25 °C, V
DD
= 3.0 V,
OSCLCN.7 = 1
—4—µA
Power Supply Sensitivity Constant Temperature — 0.05 — %/V
Temperature Sensitivity Constant Supply — 65 — ppm/°C
Table 5.9. External Oscillator Electrical Characteristics
V
DD
= 2.7 to 3.6 V; T
A
= –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
External Crystal Frequency 0.02 — 30 MHz
External CMOS Oscillator
Frequency
0—48MHz
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 46
Table 5.10. ADC0 Electrical Characteristics
V
DD
= 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
DC Accuracy
Resolution 10 bits
Integral Nonlinearity — ±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Monotonic — ±0.5 ±1 LSB
Offset Error –2 0 2 LSB
Full Scale Error –5 –2 0 LSB
Offset Temperature Coefficient — 0.005 — LSB/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion 55 58 — dB
Total Harmonic Distortion Up to the 5th harmonic — –73 — dB
Spurious-Free Dynamic Range — 78 — dB
Conversion Rate
SAR Conversion Clock — — 8.33 MHz
Conversion Time in SAR Clocks 10-bit Mode
8-bit Mode
13
11
—
—
—
—
clocks
clocks
Track/Hold Acquisition Time 300 — — ns
Throughput Rate — — 500 ksps
Analog Inputs
ADC Input Voltage Range Single Ended (AIN+ – GND) 0 — VREF V
Differential (AIN+ – AIN–) –VREF — VREF V
Absolute Pin Voltage with respect
to GND
Single Ended or Differential 0 — V
DD
V
Sampling Capacitance — 30 — pF
Input Multiplexer Impedance — 5 — k
Power Specifications
Power Supply Current
(V
DD
supplied to ADC0)
Operating Mode, 500 ksps — 750 1000 µA
Power Supply Rejection — 1 — mV/V
Note: Represents one standard deviation from the mean.
C8051F380/1/2/3/4/5/6/7/C
47 Rev. 1.5
Table 5.11. Temperature Sensor Electrical Characteristics
V
DD
= 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Linearity — ± 0.5 — °C
Slope — 2.87 — mV/°C
Slope Error* — ±120 — µV/°C
Offset Temp = 0 °C — 764 — mV
Offset Error* Temp = 0 °C — ±15 — mV
Note: Represents one standard deviation from the mean.
Table 5.12. Voltage Reference Electrical Characteristics
V
DD
= 3.0 V; –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient 2.38 2.42 2.46 V
VREF Short-Circuit Current — — 8 mA
VREF Temperature
Coefficient
—35—ppm/°C
Load Regulation Load = 0 to 200 µA to GND — 1.5 — ppm/µA
VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic bypass — 3 — ms
VREF Turn-on Time 2 0.1 µF ceramic bypass — 100 — µs
Power Supply Rejection — 140 — ppm/V
External Reference (REFBE = 0)
Input Voltage Range 1 — V
DD
V
Input Current Sample Rate = 500 ksps; VREF = 3.0 V — 9 — µA
Power Specifications
Supply Current — 75 — µA
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 48
Table 5.13. Comparator Electrical Characteristics
V
DD
= 3.0 V, –40 to +85 °C unless otherwise noted.
Parameter Test Condition Min Typ Max Unit
Response Time:
Mode 0, Vcm
*
= 1.5 V
CP0+ – CP0– = 100 mV — 100 — ns
CP0+ – CP0– = –100 mV — 250 — ns
Response Time:
Mode 1, Vcm
*
= 1.5 V
CP0+ – CP0– = 100 mV — 175 — ns
CP0+ – CP0– = –100 mV — 500 — ns
Response Time:
Mode 2, Vcm
*
= 1.5 V
CP0+ – CP0– = 100 mV — 320 — ns
CP0+ – CP0– = –100 mV — 1100 — ns
Response Time:
Mode 3, Vcm
*
= 1.5 V
CP0+ – CP0– = 100 mV — 1050 — ns
CP0+ – CP0– = –100 mV — 5200 — ns
Common-Mode Rejection Ratio — 1.5 4 mV/V
Positive Hysteresis 1 CP0HYP1–0 = 00 — 0 1 mV
Positive Hysteresis 2 CP0HYP1–0 = 01 2 5 10 mV
Positive Hysteresis 3 CP0HYP1–0 = 10 7 10 20 mV
Positive Hysteresis 4 CP0HYP1–0 = 11 15 20 30 mV
Negative Hysteresis 1 CP0HYN1–0 = 00 — 0 1 mV
Negative Hysteresis 2 CP0HYN1–0 = 01 2 5 10 mV
Negative Hysteresis 3 CP0HYN1–0 = 10 7 10 20 mV
Negative Hysteresis 4 CP0HYN1–0 = 11 15 20 30 mV
Inverting or Non-Inverting Input
Voltage Range
–0.25 — V
DD
+ 0.25 V
Input Capacitance — 4 — pF
Input Bias Current — 0.001 — nA
Input Offset Voltage –10 — +10 mV
Power Supply
Power Supply Rejection — 0.1 — mV/V
Power-up Time — 10 — µs
Supply Current at DC Mode 0 — 20 — µA
Mode 1 — 10 — µA
Mode 2 — 4 — µA
Mode 3 — 1 — µA
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
C8051F380/1/2/3/4/5/6/7/C
49 Rev. 1.5
Table 5.14. USB Transceiver Electrical Characteristics
V
DD
= 3.0 V to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Transmitter
Output High Voltage (V
OH
)2.8——V
Output Low Voltage (V
OL
)——0.8V
VBUS Detection Input Low
Voltage
—— 1.0
V
VBUS Detection Input High
Voltage
3.0 — —
V
Output Crossover Point
(V
CRS
)
1.3 — 2.0 V
Output Impedance (Z
DRV
) Driving High
Driving Low
—
—
38
38
—
—
W
Pull-up Resistance (R
PU
) Full Speed (D+ Pull-up)
Low Speed (D– Pull-up)
1.425 1.5 1.575 k
Output Rise Time (T
R
) Low Speed
Full Speed
75
4
—
—
300
20
ns
Output Fall Time (T
F
) Low Speed
Full Speed
75
4
—
—
300
20
ns
Receiver
Differential Input
Sensitivity (V
DI
)
| (D+) – (D–) | 0.2 — — V
Differential Input Common
Mode Range (V
CM
)
0.8 — 2.5 V
Input Leakage Current (I
L
) Pullups Disabled — <1.0 — µA
Note: Refer to the USB Specification for timing diagrams and symbol definitions.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 50
6. 10-Bit ADC (ADC0, C8051F380/1/2/3/C only)
ADC0 on the C8051F380/1/2/3/C is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold, and a programmable window detector. The ADC is fully configurable under soft-
ware control via Special Function Registers. The ADC may be configured to measure various different sig-
nals using the analog multiplexer described in Section “6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C
only)” on page 59. The voltage reference for the ADC is selected as described in Section “7. Voltage Refer-
ence Options” on page 62. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control
register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Figure 6.1. ADC0 Functional Block Diagram
ADC0CF
AD0LJST
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
AD0TM
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
AD0WINT
001
010
011
100
CNVSTR Input
Window
Compare
Logic
GND
101 Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AMX0P
AMX0P5
AMX0P4
AMX0P3
AMX0P2
AMX0P1
AMX0P0
AMX0N
AMX0N5
AMX0N4
AMX0N3
AMX0N2
AMX0N1
AMX0N0
AIN+
AIN-
VREF
Positive
Input
(AIN+)
AMUX
VDD
Negative
Input
(AIN-)
AMUX
Temp
Sensor
Port I/O
Pins*
Port I/O
Pins*
* 21 Selections on 32-pin package
32 Selections on 48-pin package
Timer 4 Overflow
Timer 5 Overflow
110
111
C8051F380/1/2/3/4/5/6/7/C
51 Rev. 1.5
6.1. Output Code Formatting
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below for both right-justified
and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
When in Differential Mode, conversion codes are represented as 10-bit signed 2s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-jus-
tified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to 0.
Input Voltage
(Single-Ended)
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 1023/1024 0x03FF 0xFFC0
VREF x 512/1024 0x0200 0x8000
VREF x 256/1024 0x0100 0x4000
0 0x0000 0x0000
Input Voltage
(Differential)
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 511/512 0x01FF 0x7FC0
VREF x 256/512 0x0100 0x4000
0 0x0000 0x0000
–VREF x 256/512 0xFF00 0xC000
–VREF 0xFE00 0x8000
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 52
6.2. Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 6.2. The output voltage (V
TEMP
) is the
positive ADC input when the temperature sensor is selected by bits AMX0P5-0 in register AMX0P.
Figure 6.2. Typical Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 5.10, “ADC0 Electrical Characteristics,” on page 46 for linearity specifications). For
absolute temperature measurements, gain and/or offset calibration is recommended. Typically a 1-point
calibration includes the following steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset and/or gain characteristics, and store these values in non-volatile
memory for use with subsequent temperature sensor measurements.
Figure 6.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
0-50 50 100
(Celsius)
V
TEMP
= Slope*(TEMP
C
) + Offset mV
700
800
900
1000
1100
(mV)
1200
C8051F380/1/2/3/4/5/6/7/C
53 Rev. 1.5
Figure 6.3. Temperature Sensor Error with 1-Point Calibration
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 54
6.3. Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register.
6.3.1. Starting a Conversion
A conversion can be initiated in one of several ways, depending on the programmed states of the ADC0
Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of
the following:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
6. A Timer 3 overflow
7. A Timer 4 overflow
8. A Timer 5 overflow
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2, 3, 4, or 5 overflows are used as the conversion source, Low Byte over-
flows are used if the timer is in 8-bit mode; High byte overflows are used if the timer is in 16-bit mode. See
Section “26. Timers” on page 263 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port I/O pin. When the
CNVSTR input is used as the ADC0 conversion source, the associated pin should be skipped by the Digi-
tal Crossbar. See Section “20. Port Input/Output” on page 153 for details on Port I/O configuration.
C8051F380/1/2/3/4/5/6/7/C
55 Rev. 1.5
6.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initi-
ate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins
on the rising edge of CNVSTR. See Figure 6.4 for track and convert timing details. Tracking can also be
disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-and-hold
mode is also useful when AMUX settings are frequently changed, due to the settling time requirements
described in Section “6.3.3. Settling Time Requirements” on page 56.
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
AD0TM=1
Track Convert Low Power Mode
AD0TM=0
Track or
Convert
Convert Track
Low Power
or Convert
SAR
Clocks
123456789
1
0
1
1
1
2
123456789
SAR
Clocks
B. ADC0 Timing for Internal Trigger Source
123456789
CNVSTR
(AD0CM[2:0]=100)
AD0TM=1
A. ADC0 Timing for External Trigger Source
SAR Clocks
Track or Convert Convert TrackAD0TM=0
Track Convert
Low Power
Mode
Low Power
or Convert
1
0
1
1
1
3
1
4
1
0
1
1
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 56
6.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any
external source resistance, and the accuracy required for the conversion. Note that in low-power tracking
mode, three SAR clocks are used for tracking at the start of every conversion. For most applications, these
three SAR clocks will meet the minimum tracking time requirements.
Figure 6.5 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 6.1. See Table 5.10 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
Equation 6.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
TOTAL
is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Figure 6.5. ADC0 Equivalent Input Circuits
t
2
n
SA
--------
ln R
TOTAL
C
SAMPLE
=
R
MUX
RC
Input
= R
MUX
* C
SAMPLE
R
MUX
C
SAMPLE
C
SAMPLE
MUX
Select
MUX Select
Differential Mode
Px.x
Px.x
R
MUX
C
SAMPLE
RC
Input
= R
MUX
* C
SAMPLE
MUX Select
Single-Ended Mode
Px.x
C8051F380/1/2/3/4/5/6/7/C
57 Rev. 1.5
SFR Address = 0xBC; SFR Page = All Pages
SFR Definition 6.1. ADC0CF: ADC0 Configuration
Bit76543210
Name
AD0SC[4:0] AD0LJST Reserved
Type
R/W R/W R/W
Reset
11111000
Bit Name Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
Note: If the Memory Power Controller is enabled (MPCE = '1'), AD0SC must be set to at least
"00001" for proper ADC operation.
2AD0LJSTADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
1:0 Reserved Must Write 00b.
AD0SC
SYSCLK
CLK
SAR
------------------------1–=
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 58
SFR Address = 0xBE; SFR Page = All Pages
SFR Address = 0xBD; SFR Page = All Pages
SFR Definition 6.2. ADC0H: ADC0 Data Word MSB
Bit76543210
Name
ADC0H[7:0]
Type
R/W
Reset
00000000
Bit Name Function
7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10-
bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data
Word.
SFR Definition 6.3. ADC0L: ADC0 Data Word LSB
Bit76543210
Name
ADC0L[7:0]
Type
R/W
Reset
00000000
Bit Name Function
7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will
read 000000b.
C8051F380/1/2/3/4/5/6/7/C
59 Rev. 1.5
SFR Address = 0xE8; SFR Page = All Pages; Bit-Addressable
SFR Definition 6.4. ADC0CN: ADC0 Control
Bit76543210
Name
AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM[2:0]
Type
R/W R/W R/W R/W R/W R/W
Reset
00000000
Bit Name Function
7AD0ENADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6AD0TMADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a con-
version is in progress. Conversion begins immediately on start-of-conversion event,
as defined by AD0CM[2:0].
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion
is not in progress. A start-of-conversion signal initiates three SAR clocks of additional
tracking, and then begins the conversion. Note that there is not a tracking delay when
CNVSTR is used (AD0CM[2:0] = 100).
5AD0INTADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
4AD0BUSYADC0 Busy Bit. Read:
0: ADC0 conversion is not in
progress.
1: ADC0 conversion is in prog-
ress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if
AD0CM[2:0] = 000b
3 AD0WINT ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select.
000: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
001: ADC0 start-of-conversion source is overflow of Timer 0.
010: ADC0 start-of-conversion source is overflow of Timer 2.
011: ADC0 start-of-conversion source is overflow of Timer 1.
100: ADC0 start-of-conversion source is rising edge of external CNVSTR.
101: ADC0 start-of-conversion source is overflow of Timer 3.
110: ADC0 start-of-conversion source is overflow of Timer 4.
111: ADC0 start-of-conversion source is overflow of Timer 5.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 60
6.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Address = 0xC4; SFR Page = All Pages
SFR Address = 0xC3; SFR Page = All Pages
SFR Definition 6.5. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit76543210
Name
ADC0GTH[7:0]
Type
R/W
Reset
11111111
Bit Name Function
7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit76543210
Name
ADC0GTL[7:0]
Type
R/W
Reset
11111111
Bit Name Function
7:0 ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits.
C8051F380/1/2/3/4/5/6/7/C
61 Rev. 1.5
SFR Address = 0xC6; SFR Page = All Pages
SFR Address = 0xC5; SFR Page = All Pages
SFR Definition 6.7. ADC0LTH: ADC0 Less-Than Data High Byte
Bit76543210
Name
ADC0LTH[7:0]
Type
R/W
Reset
00000000
Bit Name Function
7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit76543210
Name
ADC0LTL[7:0]
Type
R/W
Reset
00000000
Bit Name Function
7:0 ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 62
6.4.1. Window Detector Example
Figure 6.6 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 6.7 shows an example using left-justi-
fied data with the same comparison values.
Figure 6.6. ADC Window Compare Example: Right-Justified Data
Figure 6.7. ADC Window Compare Example: Left-Justified Data
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
C8051F380/1/2/3/4/5/6/7/C
63 Rev. 1.5
6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C only)
AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to
individual Port pins, the on-chip temperature sensor, or the positive power supply (V
DD
). The negative
input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the nega-
tive input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential Mode.
The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR Definition
6.9 and SFR Definition 6.10.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1
the corresponding bit in register PnSKIP. See Section “20. Port Input/Output” on page 153 for more Port
I/O configuration details.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 64
SFR Address = 0xBB; SFR Page = All Pages
SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select
Bit76543210
Name AMX0P[5:0]
Type RR R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = don’t care.
5:0 AMX0P[5:0] AMUX0 Positive Input Selection.
AMX0P 32-pin
Packages
48-pin
Packages
AMX0P 32-pin
Packages
48-pin
Packages
000000: P1.0 P2.0 010010: P0.1 P0.4
000001: P1.1 P2.1 010011: P0.4 P1.1
000010: P1.2 P2.2 010100: P0.5 P1.2
000011: P1.3 P2.3 010101: Reserved P1.0
000100: P1.4 P2.5 010110: Reserved P1.3
000101: P1.5 P2.6 010111: Reserved P1.6
000110: P1.6 P3.0 011000: Reserved P1.7
000111: P1.7 P3.1 011001: Reserved P2.4
001000: P2.0 P3.4 011010: Reserved P2.7
001001: P2.1 P3.5 011011: Reserved P3.2
001010: P2.2 P3.7 011100: Reserved P3.3
001011: P2.3 P4.0 011101: Reserved P3.6
001100: P2.4 P4.3 011110: Temp Sensor Temp Sensor
001101: P2.5 P4.4 011111: V
DD
V
DD
001110: P2.6 P4.5 100000: Reserved P4.1
001111: P2.7 P4.6 100001: Reserved P4.2
010000: P3.0 Reserved 100010: Reserved P4.7
010001: P0.0 P0.3 100011 -
111111:
Reserved Reserved
C8051F380/1/2/3/4/5/6/7/C
65 Rev. 1.5
SFR Address = 0xBA; SFR Page = All Pages
SFR Definition 6.10. AMX0N: AMUX0 Negative Channel Select
Bit76543210
Name AMX0N[5:0]
Type RR R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = don’t care.
5:0 AMX0N[5:0] AMUX0 Negative Input Selection.
AMX0N 32-pin
Packages
48-pin
Packages
AMX0N 32-pin
Packages
48-pin
Packages
000000: P1.0 P2.0 010010: P0.1 P0.4
000001: P1.1 P2.1 010011: P0.4 P1.1
000010: P1.2 P2.2 010100: P0.5 P1.2
000011: P1.3 P2.3 010101: Reserved P1.0
000100: P1.4 P2.5 010110: Reserved P1.3
000101: P1.5 P2.6 010111: Reserved P1.6
000110: P1.6 P3.0 011000: Reserved P1.7
000111: P1.7 P3.1 011001: Reserved P2.4
001000: P2.0 P3.4 011010: Reserved P2.7
001001: P2.1 P3.5 011011: Reserved P3.2
001010: P2.2 P3.7 011100: Reserved P3.3
001011: P2.3 P4.0 011101: Reserved P3.6
001100: P2.4 P4.3 011110: VREF VREF
001101: P2.5 P4.4 011111: GND
(Single-Ended
Measurement)
GND
(Single-Ended
Measurement)
001110: P2.6 P4.5 100000: Reserved P4.1
001111: P2.7 P4.6 100001: Reserved P4.2
010000: P3.0 Reserved 100010: Reserved P4.7
010001: P0.0 P0.3 100011 -
111111:
Reserved Reserved
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 66
7. Voltage Reference Options
The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage ref-
erence, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply
voltage (V
DD
), or the regulated 1.8 V internal supply (see Figure 7.1). The REFSL bit in the Reference
Control register (REF0CN, SFR Definition 7.1) selects the reference source for the ADC. For an external
source or the on-chip reference, REFSL should be set to 0 to select the VREF pin. To use V
DD
as the ref-
erence source, REFSL should be set to 1. To override this selection and use the internal regulator as the
reference source, the REGOVR bit can be set to 1.
The BIASE bit enables the internal voltage bias generator, which is used by many of the analog peripher-
als on the device. This bias is automatically enabled when any peripheral which requires it is enabled, and
it does not need to be enabled manually. The bias generator may be enabled manually by writing a 1 to the
BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in
Table 5.12.
The C8051F380/1/2/3/C devices also include an on-chip voltage reference circuit which consists of a
1.2 V, temperature stable bandgap voltage reference generator and a selectable-gain output buffer ampli-
fier. The buffer is configured for 1x or 2x gain using the REFBGS bit in register REF0CN. On the 1x gain
setting the output voltage is nominally 1.2 V, and on the 2x gain setting the output voltage is nominally
2.4 V. The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register
REF0CN to a 1. The maximum load seen by the VREF pin must be less than 200 µA to GND. Bypass
capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND, and a minimum of 0.1uF is
required. If the on-chip reference is not used, the REFBE bit should be cleared to 0. Electrical specifica-
tions for the on-chip voltage reference are given in Table 5.12.
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip ref-
erence circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “20. Port Input/Output” on page 153 for the location of the VREF pin, as well as details of
how to configure the pin in analog mode and to be skipped by the crossbar.
Figure 7.1. Voltage Reference Functional Block Diagram
To Analog Mux
VDD
VREF
R1
VDD
External
Voltage
Reference
Circuit
GND
Temp Sensor
EN
Bias Generator
To ADC, IDAC,
Internal Oscillators,
Reference,
TempSensor
EN
IOSCEN
0
1
REF0CN
REFSL
TEMPE
BIASE
REFBE
REGOVR
REFBGS
REFBE
Recommended Bypass
Capacitors
+
4.7F0.1F
VREF
(to ADC)
0
1
Internal
Regulator
REGOVR
1.2V Reference
EN
1x/2x
REFBGS
C8051F380/1/2/3/4/5/6/7/C
67 Rev. 1.5
SFR Address = 0xD1; SFR Page = All Pages
SFR Definition 7.1. REF0CN: Reference Control
Bit76543210
Name
REFBGS REGOVR REFSL TEMPE BIASE REFBE
Type
R/W R R R/W R/W R/W R/W R/W
Reset
00000000
Bit Name Function
7 REFBGS Reference Buffer Gain Select.
This bit selects between 1x and 2x gain for the on-chip voltage reference buffer.
0: 2x Gain
1: 1x Gain
6:5 Unused Read = 00b; Write = don’t care.
4REGOVRRegulator Reference Override.
This bit “overrides” the REFSL bit, and allows the internal regulator to be used as a ref-
erence source.
0: The voltage reference source is selected by the REFSL bit.
1: The internal regulator is used as the voltage reference.
3 REFSL Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: V
REF
pin used as voltage reference.
1: V
DD
used as voltage reference.
2 TEMPE Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
1 BIASE Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0 REFBE On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the V
REF
pin.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 68
8. Comparator0 and Comparator1
C8051F380/1/2/3/4/5/6/7/C devices include two on-chip programmable voltage comparators: Comparator0
is shown in Figure 8.1, Comparator1 is shown in Figure 8.2. The two comparators operate identically with
the following exceptions: (1) Their input selections differ as described in Section “8.1. Comparator Multi-
plexers” on page 71; (2) Comparator0 can be used as a reset source.
The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an
asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the sys-
tem clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “20.2. Port I/O Initialization” on page 158). Comparator0 may also be used as a
reset source (see Section “17.5. Comparator0 Reset” on page 132).
The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section
“8.1. Comparator Multiplexers” on page 71.
Figure 8.1. Comparator0 Functional Block Diagram
VDD
Reset
Decision
Tree
+
-
Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
CP0 -
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Interrupt
0
1
0
1
CP0RIF
CP0FIF
0
1
CP0EN
0
1
EA
Comparator
Input Mux
CPT0CN
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
C8051F380/1/2/3/4/5/6/7/C
69 Rev. 1.5
Figure 8.2. Comparator1 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “20.1. Priority Crossbar Decoder” on
page 154 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V
DD
) + 0.25 V without damage or upset. The complete Comparator elec-
trical specifications are given in Section “5. Electrical Characteristics” on page 41.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 8.2 and SFR Definition 8.4). Selecting a longer response time reduces the Comparator supply current.
VDD
+
-
Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP1 +
CP1 -
CPT1MD
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1
CP1A
CP1
Interrupt
0
1
0
1
CP1RIF
CP1FIF
0
1
CP1EN
0
1
EA
Comparator
Input Mux
CPT1CN
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 70
Figure 8.3. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN
(for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits 3–0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 8.1). The amount of negative hysteresis voltage is determined by the settings of
the CPnHYN bits. Settings of 20, 10 or 5 mV of nominal negative hysteresis can be programmed, or nega-
tive hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the
setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “16.1. MCU Interrupt Sources and Vectors” on page 119). The
CPnFIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by soft-
ware. The Comparator rising-edge interrupt mask is enabled by setting CPnRIE to a logic 1. The Compar-
ator falling-edge interrupt mask is enabled by setting CPnFIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-
ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
Positive Hysteresis Voltage
(Programmed with CPnHYP Bits)
Negative Hysteresis Voltage
(Programmed by CPnHYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CPn+
CPn-
CPn
VIN+
VIN-
OUT
VOH
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
OUTPUT
VOL
C8051F380/1/2/3/4/5/6/7/C
71 Rev. 1.5
SFR Address = 0x9B; SFR Page = All Pages
SFR Definition 8.1. CPT0CN: Comparator0 Control
Bit76543210
Name
CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0]
Type
R/W R R/W R/W R/W R/W
Reset
00000000
Bit Name Function
7 CP0EN Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6CP0OUTComparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5CP0RIFComparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4CP0FIFComparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 72
SFR Address = 0x9D; SFR Page = All Pages
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection
Bit76543210
Name CP0RIE CP0FIE CP0MD[1:0]
Type RRR/WR/WRR R/W
Reset 00000010
Bit Name Function
7:6 Unused Read = 00b, Write = don’t care.
5CP0RIEComparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4CP0FIEComparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
C8051F380/1/2/3/4/5/6/7/C
73 Rev. 1.5
SFR Address = 0x9A; SFR Page = All Pages
SFR Definition 8.3. CPT1CN: Comparator1 Control
Bit76543210
Name CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] CP1HYN[1:0]
Type R/W R R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 CP1EN Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6CP1OUTComparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5CP1RIFComparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4CP1FIFComparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 74
SFR Address = 0x9C; SFR Page = All Pages
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection
Bit76543210
Name CP1RIE CP1FIE CP1MD[1:0]
Type RRR/WR/WRR R/W
Reset 00000010
Bit Name Function
7:6 Unused Read = 00b, Write = don’t care.
5CP1RIEComparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4CP1FIEComparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP1MD[1:0] Comparator1 Mode Select.
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
C8051F380/1/2/3/4/5/6/7/C
75 Rev. 1.5
8.1. Comparator Multiplexers
C8051F380/1/2/3/4/5/6/7/C devices include an analog input multiplexer to connect Port I/O pins to the
comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition 8.5 and
SFR Definition 8.6). The CMXnP2–CMXnP0 bits select the Comparator positive input; the CMXnN2–CMX-
nN0 bits select the Comparator negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “20.3. General Purpose Port I/O” on page 161).
Figure 8.4. Comparator Input Multiplexer Block Diagram
+
-
CP1 +
CP1 -
GND
VDD
+
-
CP0 +
CP0 -
GND
VDD
CPT0MX
CMX0N2
CMX0N1
CMX0N0
CMX0P2
CMX0P1
CMX0P0
CPT1MX
CMX1N2
CMX1N1
CMX1N0
CMX1P2
CMX1P1
CMX1P0
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 76
SFR Address = 0x9F; SFR Page = All Pages
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection
Bit76543210
Name CMX0N[2:0] CMX0P[2:0]
Type RR/WRR/W
Reset 00000000
Bit Name Function
7 Unused Read = 0b; Write = don’t care.
6:4 CMX0N[2:0] Comparator0 Negative Input MUX Selection.
Selection 32-pin Package 48-pin Package
000: P1.1 P2.1
001: P1.5 P2.6
010: P2.1 P3.5
011: P2.5 P4.4
100: P0.1 P0.4
101-111: Reserved Reserved
3 Unused Read = 0b; Write = don’t care.
2:0 CMX0P[2:0] Comparator0 Positive Input MUX Selection.
Selection 32-pin Package 48-pin Package
000: P1.0 P2.0
001: P1.4 P2.5
010: P2.0 P3.4
011: P2.4 P4.3
100: P0.0 P0.3
101-111: Reserved Reserved
C8051F380/1/2/3/4/5/6/7/C
77 Rev. 1.5
SFR Address = 0x9E; SFR Page = All Pages
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection
Bit76543210
Name CMX1N[2:0] CMX1P[2:0]
Type RR/WRR/W
Reset 00000000
Bit Name Function
7 Unused Read = 0b; Write = don’t care.
6:4 CMX1N[2:0] Comparator1 Negative Input MUX Selection.
Selection 32-pin Package 48-pin Package
000: P1.3 P2.3
001: P1.7 P3.1
010: P2.3 P4.0
011: Reserved P4.6
100: P0.5 P1.2
101-111: Reserved Reserved
3 Unused Read = 0b; Write = don’t care.
2:0 CMX1P[2:0] Comparator1 Positive Input MUX Selection.
Selection 32-pin Package 48-pin Package
000: P1.2 P2.2
001: P1.6 P3.0
010: P2.2 P3.7
011: Reserved P4.5
100: P0.4 P1.1
101-111: Reserved Reserved
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 78
9. Voltage Regulators (REG0 and REG1)
C8051F380/1/2/3/4/5/6/7/C devices include two internal voltage regulators: one regulates a voltage source
on REGIN to 3.3 V (REG0), and the other regulates the internal core supply to 1.8 V from a V
DD
supply of
1.8 to 3.6 V (REG1). When enabled, the REG0 output appears on the V
DD
pin and can be used to power
external devices. REG0 can be enabled/disabled by software using bit REG0DIS in register REG01CN
(SFR Definition 9.1). REG1 has two power-saving modes built into the regulator to help reduce current
consumption in low-power applications. These modes are accessed through the REG01CN register. Elec-
trical characteristics for the on-chip regulators are specified in Table 5.5 on page 44.
Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered
function. REG0 configuration options are shown in “4. Typical Connection Diagrams” Figure 4.1–
Figure 4.4.
9.1. Voltage Regulator (REG0)
See “4. Typical Connection Diagrams” for typical connection diagrams using the REG0 voltage regulator.
9.1.1. Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is
degraded. See Table 5.5 for normal and low power mode supply current specifications. The REG0 mode
selection is controlled via the REG0MD bit in register REG01CN.
9.1.2. VBUS Detection
When the USB Function Controller is used (see section Section “21. Universal Serial Bus Controller
(USB0)” on page 172), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register
REG01CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be gener-
ated when the VBUS signal has either a falling or rising edge. The VBUS interrupt is edge-sensitive, and
has no associated interrupt pending flag. See Table 5.5 for VBUS input parameters.
Important Note: When USB is selected as a reset source, a system reset will be generated when a falling
or rising edge occurs on the VBUS pin. See Section “17. Reset Sources” on page 129 for details on select-
ing USB as a reset source.
9.2. Voltage Regulator (REG1)
Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode.
This allows any enabled reset source to generate a reset for the device and bring the device out of STOP
mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the inter-
nal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST
pin
and a full power cycle of the device are the only methods of generating a reset.
REG1 offers an additional low power mode intended for use when the device is in suspend mode. This low
power mode should not be used during normal operation or if the REG0 Voltage Regulator is disabled.
See Table 5.5 for normal and low power mode supply current specifications. The REG1 mode selection is
controlled via the REG1MD bit in register REG01CN.
Important Note: At least 12 clock instructions must occur after placing REG1 in low power mode before
the Internal High Frequency Oscillator is Suspended (OSCICN.5 = 1b).
C8051F380/1/2/3/4/5/6/7/C
79 Rev. 1.5
SFR Address = 0xC9; SFR Page = All Pages
SFR Definition 9.1. REG01CN: Voltage Regulator Control
Bit76543210
Name REG0DIS VBSTAT Reserved REG0MD STOPCF Reserved REG1MD Reserved
Type R/W R R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7REG0DISVoltage Regulator (REG0) Disable.
This bit enables or disables the REG0 Voltage Regulator.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
6 VBSTAT VBUS Signal Status.
This bit indicates whether the device is connected to a USB network.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
5 Reserved Must Write 0b.
4REG0MDVoltage Regulator (REG0) Mode Select.
This bit selects the Voltage Regulator mode for REG0. When REG0MD is set to 1, the
REG0 voltage regulator operates in lower power (suspend) mode.
0: REG0 Voltage Regulator in normal mode.
1: REG0 Voltage Regulator in low power mode.
3STOPCFStop Mode Configuration (REG1).
This bit configures the REG1 regulator’s behavior when the device enters STOP mode.
0: REG1 Regulator is still active in STOP mode. Any enabled reset source will reset the
device.
1: REG1 Regulator is shut down in STOP mode. Only the RST
pin or power cycle can
reset the device.
2 Reserved Must Write 0b.
1REG1MDVoltage Regulator (REG1) Mode.
This bit selects the Voltage Regulator mode for REG1. When REG1MD is set to 1, the
REG1 voltage regulator operates in lower power mode.
0: REG1 Voltage Regulator in normal mode.
1: REG1 Voltage Regulator in low power mode.
This bit should not be set to '1' if the REG0 Voltage Regulator is disabled.
0 Reserved Must Write 0b.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 80
10. Power Management Modes
The C8051F380/1/2/3/4/5/6/7/C devices have three software programmable power management modes:
Idle, Stop, and Suspend. Idle mode and stop mode are part of the standard 8051 architecture, while sus-
pend mode is an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
pend mode is similar to stop mode in that the internal oscillator is halted, but the device can wake on activ-
ity with the USB transceiver. The CPU is not halted in suspend mode, so it can run on another oscillator, if
desired. Since clocks are running in Idle mode, power consumption is dependent upon the system clock
frequency and the number of peripherals left in active mode before entering Idle. Stop mode and suspend
mode consume the least power because the majority of the device is shut down with no clocks active. SFR
Definition 10.1 describes the Power Control Register (PCON) used to control the C8051F380/1/2/3/4/5/6/
7/C's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the
OSCICN register (SFR Definition 19.3).
Although the C8051F380/1/2/3/4/5/6/7/C has Idle, Stop, and suspend modes available, more control over
the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog
peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as tim-
ers or serial buses, draw little power when they are not in use. Turning off oscillators lowers power con-
sumption considerably, at the expense of reduced functionality.
10.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON ; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “17.6. PCA Watchdog Timer
C8051F380/1/2/3/4/5/6/7/C
81 Rev. 1.5
Reset” on page 133 for more information on the use and configuration of the WDT.
10.2. Stop Mode
Setting the stop mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
By default, when in stop mode the internal regulator is still active. However, the regulator can be config-
ured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the
STOPCF bit in register REG01CN should be set to 1 prior to setting the STOP bit (see SFR Definition 9.1).
If the regulator is shut down using the STOPCF bit, only the RST
pin or a full power cycle are capable of
resetting the device.
10.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the high-frequency internal oscillator
and go into suspend mode as soon as the instruction that sets the bit completes execution. All internal reg-
isters and memory maintain their original data. The CPU is not halted in Suspend, so code can still be exe-
cuted using an oscillator other than the internal high-frequency oscillator.
Suspend mode can be terminated by resume signalling on the USB data pins, or a device reset event.
When suspend mode is terminated, if the oscillator source is the internal high-frequency oscillator, the
device will continue execution on the instruction following the one that set the SUSPEND bit. If the wake
event was configured to generate an interrupt, the interrupt will be serviced upon waking the device. If sus-
pend mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 82
SFR Address = 0x87; SFR Page = All Pages
SFR Definition 10.1. PCON: Power Control
Bit76543210
Name GF[5:0] STOP IDLE
Type R/W R/W R/W
Reset 00000000
Bit Name Function
7:2 GF[5:0] General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1STOPStop Mode Select.
Setting this bit will place the CIP-51 in stop mode. This bit will always be read as 0.
1: CPU goes into stop mode (internal oscillator stopped).
0IDLEIDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
C8051F380/1/2/3/4/5/6/7/C
83 Rev. 1.5
11. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 28), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 11.1 for a block diagram).
The CIP-51 includes the following features:
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Figure 11.1. CIP-51 Block Diagram
Fully Compatible with MCS-51 Instruction Set
48 MIPS Peak Throughput with 48 MHz Clock
0 to 48 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE
POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
D8
STACK POINTER
D8
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 84
With the CIP-51's maximum system clock at 48 MHz, it has a peak throughput of 48 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “28. C2 Interface” on page 316.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
11.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
11.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 11.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
Clocks to Execute 1 2 2/4 3 3/5 4 5 4/6 6 8
Number of Instructions 2650510652221
C8051F380/1/2/3/4/5/6/7/C
85 Rev. 1.5
Table 11.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 86
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
Table 11.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F380/1/2/3/4/5/6/7/C
87 Rev. 1.5
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
Program Flow
Timings are listed with the PFE on and FLRT = 0. Extra cycles are required for branches if FLRT = 1.
JC rel Jump if Carry is set 2 2/4
JNC rel Jump if Carry is not set 2 2/4
JB bit, rel Jump if direct bit is set 3 3/5
JNB bit, rel Jump if direct bit is not set 3 3/5
JBC bit, rel Jump if direct bit is set and clear bit 3 3/5
ACALL addr11 Absolute subroutine call 2 4
LCALL addr16 Long subroutine call 3 5
RET Return from subroutine 1 6
RETI Return from interrupt 1 6
AJMP addr11 Absolute jump 2 4
LJMP addr16 Long jump 3 5
SJMP rel Short jump (relative address) 2 4
JMP @A+DPTR Jump indirect relative to DPTR 1 4
JZ rel Jump if A equals zero 2 2/4
JNZ rel Jump if A does not equal zero 2 2/4
CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 4/6
CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/5
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal
33/5
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
equal
34/6
DJNZ Rn, rel Decrement Register and jump if not zero 2 2/4
DJNZ direct, rel Decrement direct byte and jump if not zero 3 3/5
NOP No operation 1 1
Table 11.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 88
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
C8051F380/1/2/3/4/5/6/7/C
89 Rev. 1.5
11.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sec-
tions of the datasheet associated with their corresponding system function.
SFR Address = 0x82; SFR Page = All Pages
SFR Address = 0x83; SFR Page = All Pages
SFR Definition 11.1. DPL: Data Pointer Low Byte
Bit76543210
Name DPL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
SFR Definition 11.2. DPH: Data Pointer High Byte
Bit76543210
Name DPH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 90
SFR Address = 0x81; SFR Page = All Pages
SFR Address = 0xE0; SFR Page = All Pages; Bit-Addressable
SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable
SFR Definition 11.3. SP: Stack Pointer
Bit76543210
Name SP[7:0]
Type R/W
Reset 00000111
Bit Name Function
7:0 SP[7:0] Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 11.4. ACC: Accumulator
Bit76543210
Name ACC[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 11.5. B: B Register
Bit76543210
Name B[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 B[7:0] B Register.
This register serves as a second accumulator for certain arithmetic operations.
C8051F380/1/2/3/4/5/6/7/C
91 Rev. 1.5
SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable
SFR Definition 11.6. PSW: Program Status Word
Bit76543210
Name CY AC F0 RS[1:0] OV F1 PARITY
Type R/W R/W R/W R/W R/W R/W R
Reset 00000000
Bit Name Function
7CYCarry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6ACAuxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5F0User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3 RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2OVOverflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1F1User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
0PARITYParity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 92
12. Prefetch Engine
The C8051F380/1/2/3/4/5/6/7/C family of devices incorporate a 2-byte prefetch engine. Because the
access time of the Flash memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch
engine is necessary for code execution above 25 MHz. When operating at speeds greater than 25 MHz,
the prefetch engine must be enabled by setting PFE0CN.PFEN and FLSCL.FLRT to 1. Instructions are
read from Flash memory two bytes at a time by the prefetch engine and given to the CIP-51 processor
core to execute. When running linear code (code without any jumps or branches), the prefetch engine
allows instructions to be executed at full speed. When a code branch occurs, the processor may be stalled
for up to two clock cycles while the next set of code bytes is retrieved from Flash memory. It is recom-
mended that the prefetch be used for optimal code execution timing.
Note: The prefetch engine can be disabled when the device is in suspend mode to save power.
SFR Address = 0xAF; SFR Page = All Pages
SFR Definition 12.1. PFE0CN: Prefetch Engine Control
Bit76543210
Name PFEN FLBWE
Type RRR/WRRRRR/W
Reset 00100000
Bit Name Function
7:6 Unused Read = 00b, Write = don’t care.
5PFENPrefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
4:1 Unused Read = 0000b. Write = don’t care.
0FLBWEFlash Block Write Enable.
This bit allows block writes to Flash memory from software.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
C8051F380/1/2/3/4/5/6/7/C
93 Rev. 1.5
13. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 13.1 and Figure 13.2.
Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F380/1/4/5)
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
0x0000
0x0FFF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x0400
0xFFFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0xFC00
0xFBFF
USB FIFOs
1024 Bytes
0x07FF
0x1000
0xFFFF
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 94
Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F382/3/6/7)
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 2048 Bytes
(Accessable using MOVX
instruction)
0x0000
0x07FF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x0400
0xFFFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x7FFF
USB FIFOs
1024 Bytes
0x07FF
0x0800
C8051F380/1/2/3/4/5/6/7/C
95 Rev. 1.5
Figure 13.3. On-Chip Memory Map for 16 kB Devices (C8051F38C)
13.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F380/1/2/3/4/5/6/7/C implements
64 kB, 32 kB, or 16 kB of this program memory space as in-system, re-programmable Flash memory. Note
that on the C8051F380/1/4/5 (64 kB version), addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature
provides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to Section “18. Flash Memory” on page 135 for further details.
13.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory.
Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations
0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x3FFF
XRAM - 2048 Bytes
(Accessable using MOVX
instruction)
0x0000
0x07FF
Off-Chip XRAM
(Available only on devices
with EMIF)
0xFFFF
0x0800
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
0x0400
USB FIFOs
1024 Bytes
0x07FF
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 96
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 13.1 illustrates the data memory organization of the CIP-51.
13.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 11.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
13.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
13.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
C8051F380/1/2/3/4/5/6/7/C
97 Rev. 1.5
14. External Data Memory Interface and On-Chip XRAM
4 kB (C8051F380/1/4/5) or 2 kB (C8051F382/3/6/7/C) of RAM are included on-chip, and mapped into the
external data memory space (XRAM). The 1 kB of USB FIFO space can also be mapped into XRAM
address space for additional general-purpose data storage. Additionally, an External Memory Interface
(EMIF) is available on the C8051F380/2/4/6 devices, which can be used to access off-chip data memories
and memory-mapped devices connected to the GPIO ports. The external memory space may be accessed
using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect
addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as
@R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Reg-
ister (EMI0CN, shown in SFR Definition 14.1). Note: the MOVX instruction can also be used for writing to
the FLASH memory. See Section “18. Flash Memory” on page 135 for details. The MOVX instruction
accesses XRAM by default.
14.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
14.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV DPTR, #1234h ; load DPTR with 16-bit address to read (0x1234)
MOVX A, @DPTR ; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
14.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper
8-bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of
the effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV EMI0CN, #12h ; load high byte of address into EMI0CN
MOV R0, #34h ; load low byte of address into R0 (or R1)
MOVX a, @R0 ; load contents of 0x1234 into accumulator A
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 98
14.2. Accessing USB FIFO Space
The C8051F380/1/2/3/4/5/6/7/C include 1k of RAM which functions as USB FIFO space. Figure 14.1
shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB
FIFO registers; see Section “21.5. FIFO Management” on page 181 for more information on accessing
these FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space.
Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO
block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing
USB FIFO space.
To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the
USBFAE bit in register EMI0CF must be set to 1, and (2) the USB clock must be greater than or equal to
twice the SYSCLK (USBCLK >
2 x SYSCLK). When this bit is set, the USB FIFO space is mapped into
XRAM space at addresses 0x0400 to 0x07FF. The normal XRAM (on-chip or external) at the same
addresses cannot be accessed when the USBFAE bit is set to 1.
Important Note: The USB clock must be active when accessing FIFO space.
Figure 14.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’
On/Off-Chip XRAM
0x0000
Endpoint0
(64 bytes)
Free
(64 bytes)
0x0400
0x043F
0x0440
0x063F
0x0640
0x073F
0x0740
0x07BF
0x07C0
0x07FF
Endpoint1
(128 bytes)
Endpoint2
(256 bytes)
Endpoint3
(512 bytes)
USB FIFO Space
(USB Clock Domain)
0x03FF
On/Off-Chip XRAM
0x0800
0xFFFF
C8051F380/1/2/3/4/5/6/7/C
99 Rev. 1.5
14.3. Configuring the External Memory Interface
Configuring the External Memory Interface consists of five steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is
most common), and skip the associated pins in the crossbar.
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select Multiplexed mode or Non-multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
off-chip only).
5. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 14.5.
14.4. Port Configuration
The External Memory Interface appears on Ports 4, 3, 2, and 1 when it is used for off-chip memory access.
When the EMIF is used, the Crossbar should be configured to skip over the control lines P1.7 (WR
), P1.6
(RD
), and if multiplexed mode is selected P1.3 (ALE) using the P1SKIP register. For more information
about configuring the Crossbar, see Section “Figure 20.1. Port I/O Functional Block Diagram (Port 0
through Port 3)” on page 153.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar settings for those pins. See Section “20. Port Input/Out-
put” on page 153 for more information about the Crossbar and Port operation and configuration. The Port
latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant
state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 100
SFR Address = 0xAA; SFR Page = All Pages
SFR Definition 14.1. EMI0CN: External Memory Interface Control
Bit7654321 0
Name PGSEL[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 PGSEL[7:0] XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data mem-
ory address when using an 8-bit MOVX command, effectively selecting a 256-byte
page of RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
C8051F380/1/2/3/4/5/6/7/C
101 Rev. 1.5
SFR Address = 0x85; SFR Page = All Pages
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration
Bit7654321 0
Name USBFAE EMD2 EMD[1:0] EALE[1:0]
Type RR/WRR/W R/W R/W
Reset 0000001 1
Bit Name Function
7 Unused Read = 0b; Write = don’t care.
6 USBFAE USB FIFO Access Enable.
0: USB FIFO RAM not available through MOVX instructions.
1: USB FIFO RAM available using MOVX instructions. The 1k of USB RAM will be
mapped in XRAM space at addresses 0x0400 to 0x07FF. The USB clock must be
active and greater than or equal to twice the SYSCLK (USBCLK >
2 x
SYSCLK) to access this area with MOVX instructions.
5 Unused Read = 0b; Write = don’t care.
4EMD2EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
3:2 EMD[1:0] EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses
alias to on-chip memory space.
01: Split Mode without Bank Select: Accesses below the on-chip XRAM boundary
are directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the current contents of the Address
High port latches to resolve upper address byte. Note that in order to access
off-chip space, EMI0CN must be set to a page that is not contained in the on-chip
address space.
10: Split Mode with Bank Select: Accesses below the on-chip XRAM boundary are
directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine
the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visi-
ble to the CPU.
1:0 EALE[1:0] ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 102
14.5. Multiplexed and Non-multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode,
depending on the state of the EMD2 (EMI0CF.4) bit.
14.5.1. Multiplexed Configuration
In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in
Figure 14.2.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are pre-
sented to AD[7:0]. During this phase, the address latch is configured such that the ‘Q’ outputs reflect the
states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD
or WR is asserted.
See Section “14.7.2. Multiplexed Mode” on page 111 for more information.
Figure 14.2. Multiplexed Configuration Example
14.5.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a
Non-multiplexed Configuration is shown in Figure 14.3. See Section “14.7.1. Non-multiplexed Mode” on
page 108 for more information about Non-multiplexed operation.
ADDRESS/DATA BUS
ADDRESS BUS
E
M
I
F
A[15:8]
AD[7:0]
WR
RD
ALE
64K X 8
SRAM
OE
WE
I/O[7:0]
74HC373
G
DQ
A[15:8]
A[7:0]
CE
V
DD
8
(Optional)
C8051F380/1/2/3/4/5/6/7/C
103 Rev. 1.5
Figure 14.3. Non-multiplexed Configuration Example
ADDRESS BUS
E
M
I
F
A[15:0]
64K X 8
SRAM
A[15:0]
DATA BUSD[7:0] I/O[7:0]
V
DD
8
WR
RD OE
WE
CE
(Optional)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 104
14.6. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 14.4, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 14.5). These modes are summarized below.
More information about the different modes can be found in Section “14.7. Timing” on page 106.
Figure 14.4. EMIF Operating Modes
14.6.1. Internal XRAM Only
When EMI0CF.[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device.
Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending
on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both evaluate to
address 0x0000 in on-chip XRAM space.
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
14.6.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and
off-chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
EMI0CF[3:2] = 00
0xFFFF
0x0000
EMI0CF[3:2] = 11
0xFFFF
0x0000
EMI0CF[3:2] = 01
0xFFFF
0x0000
EMI0CF[3:2] = 10
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
On-Chip XRAM
0xFFFF
0x0000
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
Off-Chip
Memory
C8051F380/1/2/3/4/5/6/7/C
105 Rev. 1.5
14.6.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and
off-chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the
lower 8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus
A[15:0] are driven in “Bank Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
14.6.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the
internal XRAM size boundary.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 106
14.7. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD
and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 14.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD
or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 for ALE
+ 1 for RD or WR + 4). The programmable setup and hold times
default to the maximum delay settings after a reset. Table 14.1 lists the AC parameters for the External
Memory Interface, and Figure 14.5 through Figure 14.10 show the timing diagrams for the different Exter-
nal Memory Interface modes and MOVX operations.
C8051F380/1/2/3/4/5/6/7/C
107 Rev. 1.5
SFR Address = 0x84; SFR Page = All Pages
SFR Definition 14.3. EMI0TC: External Memory TIming Control
Bit7654321 0
Name EAS[1:0] EWR[3:0] EAH[1:0]
Type R/W R/W R/W
Reset 1111111 1
Bit Name Function
7:6 EAS[1:0] EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
5:2 EWR[3:0] EMIF WR
and RD Pulse-Width Control Bits.
0000: WR
and RD pulse width = 1 SYSCLK cycle.
0001: WR
and RD pulse width = 2 SYSCLK cycles.
0010: WR
and RD pulse width = 3 SYSCLK cycles.
0011: WR
and RD pulse width = 4 SYSCLK cycles.
0100: WR
and RD pulse width = 5 SYSCLK cycles.
0101: WR
and RD pulse width = 6 SYSCLK cycles.
0110: WR
and RD pulse width = 7 SYSCLK cycles.
0111: WR
and RD pulse width = 8 SYSCLK cycles.
1000: WR
and RD pulse width = 9 SYSCLK cycles.
1001: WR
and RD pulse width = 10 SYSCLK cycles.
1010: WR
and RD pulse width = 11 SYSCLK cycles.
1011: WR
and RD pulse width = 12 SYSCLK cycles.
1100: WR
and RD pulse width = 13 SYSCLK cycles.
1101: WR
and RD pulse width = 14 SYSCLK cycles.
1110: WR
and RD pulse width = 15 SYSCLK cycles.
1111: WR
and RD pulse width = 16 SYSCLK cycles.
1:0 EAH[1:0] EMIF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 108
14.7.1. Non-multiplexed Mode
14.7.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111
Figure 14.5. Non-Multiplexed 16-bit MOVX Timing
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from DPLP3
P2
P1.7
P1.6
P4 EMIF WRITE DATA
P3
P2
P1.7
P1.6
P4
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WR
RD
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from DPLP3
P2
P1.6
P1.7
P4
P3
P2
P1.6
P1.7
P4
T
ACH
T
RDH
T
ACW
T
ACS
T
RDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
RD
WR
EMIF READ DATA
Nonmuxed 16-bit WRITE
Nonmuxed 16-bit READ
C8051F380/1/2/3/4/5/6/7/C
109 Rev. 1.5
14.7.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111
Figure 14.6. Non-multiplexed 8-bit MOVX without Bank Select Timing
EMIF ADDRESS (8 LSBs) from R0 or R1P3
P2
P1.7
P1.6
P4 EMIF WRITE DATA
P3
P1.7
P1.6
P4
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WR
RD
EMIF ADDRESS (8 LSBs) from R0 or R1P3
P2
P1.6
P1.7
P4
P3
P1.6
P1.7
P4
T
ACH
T
RDH
T
ACW
T
ACS
T
RDS
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
RD
WR
EMIF READ DATA
Nonmuxed 8-bit WRITE without Bank Select
Nonmuxed 8-bit READ without Bank Select
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 110
14.7.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110
Figure 14.7. Non-multiplexed 8-bit MOVX with Bank Select Timing
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.7
P1.6
P1.3
P1.7
P1.6
P1.3
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.6
P1.7
P1.3
P1.6
P1.7
P1.3
T
ACH
T
ACW
T
ACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
T
RDH
T
RDS
EMIF READ DATA
Muxed 8-bit WRITE with Bank Select
Muxed 8-bit READ with Bank Select
C8051F380/1/2/3/4/5/6/7/C
111 Rev. 1.5
14.7.2. Multiplexed Mode
14.7.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011
Figure 14.8. Multiplexed 16-bit MOVX Timing
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.7
P1.6
P1.3
P1.7
P1.6
P1.3
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from DPH
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
DPL
T
ALEH
T
ALEL
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.6
P1.7
P1.3
P1.6
P1.7
P1.3
T
ACH
T
ACW
T
ACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
T
ALEH
T
ALEL
T
RDH
T
RDS
EMIF READ DATA
Muxed 16-bit WRITE
Muxed 16-bit READ
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 112
14.7.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011
Figure 14.9. Multiplexed 8-bit MOVX without Bank Select Timing
P4
P3
P4
ADDR[15:8]
AD[7:0]
P1.7
P1.6
P1.3
P1.7
P1.6
P1.3
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ALE
WR
RD
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
P4
P3
P4
ADDR[15:8]
AD[7:0]
P1.6
P1.7
P1.3
P1.6
P1.7
P1.3
T
ACH
T
ACW
T
ACS
ALE
RD
WR
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
T
RDH
T
RDS
EMIF READ DATA
Muxed 8-bit WRITE Without Bank Select
Muxed 8-bit READ Without Bank Select
C8051F380/1/2/3/4/5/6/7/C
113 Rev. 1.5
14.7.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010
Figure 14.10. Multiplexed 8-bit MOVX with Bank Select Timing
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.7
P1.6
P1.3
P1.7
P1.6
P1.3
T
ACH
T
WDH
T
ACW
T
ACS
T
WDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
P4
P3
P4
ADDR[15:8]
AD[7:0]
P3
P1.6
P1.7
P1.3
P1.6
P1.7
P1.3
T
ACH
T
ACW
T
ACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
T
RDH
T
RDS
EMIF READ DATA
Muxed 8-bit WRITE with Bank Select
Muxed 8-bit READ with Bank Select
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 114
Table 14.1. AC Parameters for External Memory Interface
Parameter Description Min* Max* Units
T
ACS
Address/Control Setup Time 0 3 x T
SYSCLK
ns
T
ACW
Address/Control Pulse Width 1 x T
SYSCLK
16 x T
SYSCLK
ns
T
ACH
Address/Control Hold Time 0 3 x T
SYSCLK
ns
T
ALEH
Address Latch Enable High Time 1 x T
SYSCLK
4xT
SYSCLK
ns
T
ALEL
Address Latch Enable Low Time 1 x T
SYSCLK
4xT
SYSCLK
ns
T
WDS
Write Data Setup Time 1 x T
SYSCLK
19 x T
SYSCLK
ns
T
WDH
Write Data Hold Time 0 3 x T
SYSCLK
ns
T
RDS
Read Data Setup Time 20 ns
T
RDH
Read Data Hold Time 0 ns
Note: T
SYSCLK
is equal to one period of the device system clock (SYSCLK).
C8051F380/1/2/3/4/5/6/7/C
115 Rev. 1.5
15. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F380/1/2/3/4/5/6/7/C's resources
and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as
well as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F380/1/2/3/4/5/6/7/C. This allows the addition of new functionality while retaining compatibility with
the MCS-51™ instruction set. Table 15.1
lists the SFRs implemented in the C8051F380/1/2/3/4/5/6/7/C
device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 15.2, for a detailed description of each register.
15.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F380/1/2/3/4/5/6/7/C devices utilize two SFR pages: 0x0,
and 0xF. Most SFRs are available on both pages. SFR pages are selected using the Special Function
Register Page Selection register, SFRPAGE. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
Important Note: When reading or writing SFRs that are not available on all pages within an ISR, it is rec-
ommended to save the state of the SFRPAGE register on ISR entry, and restore state on exit.
SFR Address = 0xBF; SFR Page = All Pages
SFR Definition 15.1. SFRPAGE: SFR Page
Bit7654321 0
Name
SFRPAGE[7:0]
Type
R/W
Reset
0000000 0
Bit Name Function
7:0 SFRPAGE[7:0] SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 116
Table 15.1. Special Function Register (SFR) Memory Map
Address
Page
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
F0 B P0MDIN P1MDIN P2MDIN P3MDIN P4MDIN EIP1 EIP2
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0
0
ACC XBR0 XBR1 XBR2
IT01CF
SMOD1 EIE1 EIE2
FCKCON1
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 P3SKIP
D0 PSW REF0CN SCON1 SBUF1 P0SKIP P1SKIP P2SKIP USB0XCN
C8
0 TMR2CN
REG01CN
TMR2RLL TMR2RLH TMR2L TMR2H SMB0ADM SMB0ADR
F TMR5CN TMR5RLL TMR5RLH TMR5L TMR5H SMB1ADM SMB1ADR
C0
0 SMB0CN SMB0CF SMB0DAT
ADC0GTL ADC0GTH ADC0LTL ADC0LTH P4
F SMB1CN SMB1CF SMB1DAT
B8
0
IP
CLKMUL
AMX0N AMX0P
ADC0CF
ADC0L ADC0H SFRPAGE
F SMBTC
B0 P3 OSCXCN OSCICN OSCICL SBRLL1 SBRLH1 FLSCL FLKEY
A8 IE CLKSEL EMI0CN SBCON1 P4MDOUT PFE0CN
A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT
98 SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX CPT0MX
90
0
P1
TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H
USB0ADR USB0DAT
F TMR4CN TMR4RLL TMR4RLH TMR4L TMR4H
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 P0 SP DPL DPH EMI0TC EMI0CF OSCLCN PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
Notes:
1.
SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
2. Unless indicated otherwise, SFRs are available on both page 0 and page F.
C8051F380/1/2/3/4/5/6/7/C
117 Rev. 1.5
Table 15.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Page Description Page
ACC
0xE0 All Pages Accumulator 90
ADC0CF
0xBC All Pages ADC0 Configuration 57
ADC0CN
0xE8 All Pages ADC0 Control 59
ADC0GTH
0xC4 All Pages ADC0 Greater-Than Compare High 60
ADC0GTL
0xC3 All Pages ADC0 Greater-Than Compare Low 60
ADC0H
0xBE All Pages ADC0 High 58
ADC0L
0xBD All Pages ADC0 Low 58
ADC0LTH
0xC6 All Pages ADC0 Less-Than Compare Word High 61
ADC0LTL
0xC5 All Pages ADC0 Less-Than Compare Word Low 61
AMX0N
0xBA All Pages AMUX0 Negative Channel Select 65
AMX0P
0xBB All Pages AMUX0 Positive Channel Select 64
B
0xF0 All Pages B Register 90
CKCON
0x8E All Pages Clock Control 264
CKCON1
0xE4 F Clock Control 1 265
CLKMUL
0xB9 0 Clock Multiplier 147
CLKSEL
0xA9 All Pages Clock Select 144
CPT0CN
0x9B All Pages Comparator0 Control 71
CPT0MD
0x9D All Pages Comparator0 Mode Selection 72
CPT0MX
0x9F All Pages Comparator0 MUX Selection 76
CPT1CN
0x9A All Pages Comparator1 Control 73
CPT1MD
0x9C All Pages Comparator1 Mode Selection 74
CPT1MX
0x9E All Pages Comparator1 MUX Selection 77
DPH
0x83 All Pages Data Pointer High 89
DPL
0x82 All Pages Data Pointer Low 89
EIE1
0xE6 All Pages Extended Interrupt Enable 1 123
EIE2
0xE7 All Pages Extended Interrupt Enable 2 125
EIP1
0xF6 All Pages Extended Interrupt Priority 1 124
EIP2
0xF7 All Pages Extended Interrupt Priority 2 126
EMI0CF
0x85 All Pages External Memory Interface Configuration 101
EMI0CN
0xAA All Pages External Memory Interface Control 100
EMI0TC
0x84 All Pages External Memory Interface Timing 107
FLKEY
0xB7 All Pages Flash Lock and Key 140
FLSCL
0xB6 All Pages Flash Scale 141
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 118
IE
0xA8 All Pages Interrupt Enable 121
IP
0xB8 All Pages Interrupt Priority 122
IT01CF
0xE4 0 INT0/INT1 Configuration 128
OSCICL
0xB3 All Pages Internal Oscillator Calibration 145
OSCICN
0xB2 All Pages Internal Oscillator Control 146
OSCLCN
0x86 All Pages Internal Low-Frequency Oscillator Control 148
OSCXCN
0xB1 All Pages External Oscillator Control 152
P0
0x80 All Pages Port 0 Latch 162
P0MDIN
0xF1 All Pages Port 0 Input Mode Configuration 162
P0MDOUT
0xA4 All Pages Port 0 Output Mode Configuration 163
P0SKIP
0xD4 All Pages Port 0 Skip 163
P1
0x90 All Pages Port 1 Latch 164
P1MDIN
0xF2 All Pages Port 1 Input Mode Configuration 164
P1MDOUT
0xA5 All Pages Port 1 Output Mode Configuration 165
P1SKIP
0xD5 All Pages Port 1 Skip 165
P2
0xA0 All Pages Port 2 Latch 166
P2MDIN
0xF3 All Pages Port 2 Input Mode Configuration 166
P2MDOUT
0xA6 All Pages Port 2 Output Mode Configuration 167
P2SKIP
0xD6 All Pages Port 2 Skip 167
P3
0xB0 All Pages Port 3 Latch 168
P3MDIN
0xF4 All Pages Port 3 Input Mode Configuration 168
P3MDOUT
0xA7 All Pages Port 3 Output Mode Configuration 169
P3SKIP
0xDF All Pages Port 3Skip 169
P4
0xC7 All Pages Port 4 Latch 170
P4MDIN
0xF5 All Pages Port 4 Input Mode Configuration 170
P4MDOUT
0xAE All Pages Port 4 Output Mode Configuration 171
PCA0CN
0xD8 All Pages PCA Control 311
PCA0CPH0
0xFC All Pages PCA Capture 0 High 315
PCA0CPH1
0xEA All Pages PCA Capture 1 High 315
PCA0CPH2
0xEC All Pages PCA Capture 2 High 315
PCA0CPH3
0xEE All Pages PCA Capture 3High 315
PCA0CPH4
0xFE All Pages PCA Capture 4 High 315
PCA0CPL0
0xFB All Pages PCA Capture 0 Low 315
PCA0CPL1
0xE9 All Pages PCA Capture 1 Low 315
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Page Description Page
C8051F380/1/2/3/4/5/6/7/C
119 Rev. 1.5
PCA0CPL2
0xEB All Pages PCA Capture 2 Low 315
PCA0CPL3
0xED All Pages PCA Capture 3 Low 315
PCA0CPL4
0xFD All Pages PCA Capture 4 Low 315
PCA0CPM0
0xDA All Pages PCA Module 0 Mode Register 313
PCA0CPM1
0xDB All Pages PCA Module 1 Mode Register 313
PCA0CPM2
0xDC All Pages PCA Module 2 Mode Register 313
PCA0CPM3
0xDD All Pages PCA Module 3 Mode Register 313
PCA0CPM4
0xDE All Pages PCA Module 4 Mode Register 313
PCA0H
0xFA All Pages PCA Counter High 314
PCA0L
0xF9 All Pages PCA Counter Low 314
PCA0MD
0xD9 All Pages PCA Mode 312
PCON
0x87 All Pages Power Control 82
PFE0CN
0xAF All Pages Prefetch Engine Control 92
PSCTL
0x8F All Pages Program Store R/W Control 139
PSW
0xD0 All Pages Program Status Word 91
REF0CN
0xD1 All Pages Voltage Reference Control 67
REG01CN
0xC9 All Pages Voltage Regulator 0 and 1 Control 79
RSTSRC
0xEF All Pages Reset Source Configuration/Status 134
SBCON1
0xAC All Pages UART1 Baud Rate Generator Control 248
SBRLH1
0xB5 All Pages UART1 Baud Rate Generator High 248
SBRLL1
0xB4 All Pages UART1 Baud Rate Generator Low 249
SBUF0
0x99 All Pages UART0 Data Buffer 238
SBUF1
0xD3 All Pages UART1 Data Buffer 247
SCON0
0x98 All Pages UART0 Control 237
SCON1
0xD2 All Pages UART1 Control 245
SFRPAGE
0xBF All Pages SFR Page Select 115
SMB0ADM
0xCE 0 SMBus0 Address Mask 219
SMB0ADR
0xCF 0 SMBus0 Address 218
SMB0CF
0xC1 0 SMBus0 Configuration 211
SMB0CN
0xC0 0 SMBus0 Control 215
SMB0DAT
0xC2 0 SMBus0 Data 221
SMB1ADM
0xCE F SMBus1 Address Mask 220
SMB1ADR
0xCF F SMBus1 Address 219
SMB1CF
0xC1 F SMBus1 Configuration 211
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Page Description Page
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 120
SMB1CN
0xC0 F SMBus1 Control 216
SMB1DAT
0xC2 F SMBus1 Data 222
SMBTC
0xB9 F SMBus0/1 Timing Control 213
SMOD1
0xE5 All Pages UART1 Mode 246
SP
0x81 All Pages Stack Pointer 90
SPI0CFG
0xA1 All Pages SPI Configuration 257
SPI0CKR
0xA2 All Pages SPI Clock Rate Control 259
SPI0CN
0xF8 All Pages SPI Control 258
SPI0DAT
0xA3 All Pages SPI Data 259
TCON
0x88 All Pages Timer/Counter Control 270
TH0
0x8C All Pages Timer/Counter 0 High 273
TH1
0x8D All Pages Timer/Counter 1 High 273
TL0
0x8A All Pages Timer/Counter 0 Low 272
TL1
0x8B All Pages Timer/Counter 1 Low 272
TMOD
0x89 All Pages Timer/Counter Mode 271
TMR2CN
0xC8 0 Timer/Counter 2 Control 278
TMR2H
0xCD 0 Timer/Counter 2 High 280
TMR2L
0xCC 0 Timer/Counter 2 Low 279
TMR2RLH
0xCB 0 Timer/Counter 2 Reload High 279
TMR2RLL
0xCA 0 Timer/Counter 2 Reload Low 279
TMR3CN
0x91 0 Timer/Counter 3 Control 285
TMR3H
0x95 0 Timer/Counter 3 High 287
TMR3L
0x94 0 Timer/Counter 3 Low 286
TMR3RLH
0x93 0 Timer/Counter 3 Reload High 286
TMR3RLL
0x92 0 Timer/Counter 3 Reload Low 286
TMR4CN
0x91 F Timer/Counter 4 Control 290
TMR4H
0x95 F Timer/Counter 4 High 292
TMR4L
0x94 F Timer/Counter 4 Low 291
TMR4RLH
0x93 F Timer/Counter 4 Reload High 291
TMR4RLL
0x92 F Timer/Counter 4 Reload Low 291
TMR5CN
0xC8 F Timer/Counter 5 Control 295
TMR5H
0xCD F Timer/Counter 5 High 297
TMR5L
0xCC F Timer/Counter 5 Low 296
TMR5RLH
0xCB F Timer/Counter 5 Reload High 296
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Page Description Page
C8051F380/1/2/3/4/5/6/7/C
121 Rev. 1.5
TMR5RLL
0xCA F Timer/Counter 5 Reload Low 296
USB0ADR
0x96 All Pages USB0 Indirect Address Register 176
USB0DAT
0x97 All Pages USB0 Data Register 177
USB0XCN
0xD7 All Pages USB0 Transceiver Control 174
VDM0CN
0xFF All Pages V
DD
Monitor Control 132
XBR0
0xE1 All Pages Port I/O Crossbar Control 0 159
XBR1
0xE2 All Pages Port I/O Crossbar Control 1 160
XBR2
0xE3 All Pages Port I/O Crossbar Control 2 161
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Page Description Page
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 122
16. Interrupts
The C8051F380/1/2/3/4/5/6/7/C include an extended interrupt system supporting multiple interrupt sources
with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs
pins varies according to the specific version of the device. Each interrupt source has one or more associ-
ated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid inter-
rupt condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE, EIE1, or EIE2). However, interrupts must first be globally enabled by setting the
EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0
disables all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruc-
tion that has two or more opcode bytes. Using EA (global interrupt enable) as an example:
// in 'C':
EA = 0; // clear EA bit.
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction
which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruc-
tion, the interrupt may be taken. However, a read of the enable bit will return a 0 inside the interrupt service
routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
C8051F380/1/2/3/4/5/6/7/C
123 Rev. 1.5
16.1. MCU Interrupt Sources and Vectors
The C8051F380/1/2/3/4/5/6/7/C MCUs support several interrupt sources. Software can simulate an inter-
rupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt
request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending
flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in
Table 16.1. Refer to the datasheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
16.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed prior-
ity order is used to arbitrate, given in Table 16.1.
16.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write operations and USB FIFO MOVX accesses. Interrupt ser-
vice latency will be increased for interrupts occurring while the CPU is stalled. The latency for these situa-
tions will be determined by the standard interrupt service procedure (as described above) and the amount
of time the CPU is stalled.
16.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 124
Table 16.1. Interrupt Summary
Interrupt Source Interrupt
Vector
Priority
Order
Pending Flag
Bit
Address?
Cleared
by HW?
Enable
Flag
Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled
Always
Highest
External Interrupt 0
(INT0
)
0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1
(INT1
)
0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4 RI0 (SCON0.0)
TI0 (SCON0.1)
Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow 0x002B 5 TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
Y N ET2 (IE.5) PT2 (IP.5)
SPI0 0x0033 6 SPIF (SPI0CN.7)
WCOL
(SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y N ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0 0x003B 7 SI (SMB0CN.0) Y N ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
USB0 0x0043 8 Special N N EUSB0
(EIE1.1)
PUSB0
(EIP1.1)
ADC0 Window Com-
pare
0x004B 9 AD0WINT
(ADC0CN.3)
Y N EWADC0
(EIE1.2)
PWADC0
(EIP1.2)
ADC0 Conversion
Complete
0x0053 10 AD0INT (ADC0CN.5) Y N EADC0
(EIE1.3)
PADC0
(EIP1.3)
Programmable
Counter Array
0x005B 11 CF (PCA0CN.7)
CCFn (PCA0CN.n)
Y N EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
Comparator0 0x0063 12 CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
N N ECP0
(EIE1.5)
PCP0
(EIP1.5)
Comparator1 0x006B 13 CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
N N ECP1
(EIE1.6)
PCP1
(EIP1.6)
Timer 3 Overflow 0x0073 14 TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
NN ET3
(EIE1.7)
PT3
(EIP1.7)
VBUS Level 0x007B 15 N/A N/A N/A EVBUS
(EIE2.0)
PVBUS
(EIP2.0)
UART1 0x0083 16 RI1 (SCON1.0)
TI1 (SCON1.1)
NN ES1
(EIE2.1)
PS1
(EIP2.1)
Reserved 0x008B 17 N/A N/A N/A N/A N/A
SMB1 0x0093 18 SI (SMB1CN.0) Y N ESMB1
(EIE2.3)
PSMB1
(EIP2.3)
Timer 4 Overflow 0x009B 19 TF4H (TMR4CN.7)
TF4L (TMR4CN.6)
NN ET4
(EIE2.4)
PT4
(E!P2.4)
Timer 5 Overflow 0x00A3 20 TF5H (TMR5CN.7)
TF5L (TMR5CN.6)
YN ET5
(EIE2.5)
PT5
(E!P2.5)
C8051F380/1/2/3/4/5/6/7/C
125 Rev. 1.5
SFR Address = 0xA8; SFR Page = All Pages; Bit-Addressable
SFR Definition 16.1. IE: Interrupt Enable
Bit76543210
Name
EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7EAEnable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6 ESPI0
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5ET2
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4 ES0
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3ET1
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2 EX1
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1
input.
1ET0
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0 EX0
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0
input.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 126
SFR Address = 0xB8; SFR Page = All Pages; Bit-Addressable
SFR Definition 16.2. IP: Interrupt Priority
Bit76543210
Name
PSPI0 PT2 PS0 PT1 PX1 PT0 PX0
Type R R/W R/W R/W R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7 Unused Read = 1b, Write = Don't Care.
6 PSPI0
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4 PS0
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
3PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2 PX1
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0 PX0
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
C8051F380/1/2/3/4/5/6/7/C
127 Rev. 1.5
SFR Address = 0xE6; SFR Page = All Pages
SFR Definition 16.3. EIE1: Extended Interrupt Enable 1
Bit76543210
Name
ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ET3Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6ECP1
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
5ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4 EPCA0
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3 EADC0
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2EWADC0
Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1EUSB0
Enable USB (USB0) Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
0 ESMB0
Enable SMBus0 Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 128
SFR Address = 0xF6; SFR Page = All Pages
SFR Definition 16.4. EIP1: Extended Interrupt Priority 1
Bit76543210
Name
PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PT3Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6PCP1
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
5PCP0
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4 PPCA0
Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3 PADC0
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2PWADC0
ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1PUSB0
USB (USB0) Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
0 PSMB0
SMBus0 Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
C8051F380/1/2/3/4/5/6/7/C
129 Rev. 1.5
SFR Address = 0xE7; SFR Page = All Pages
SFR Definition 16.5. EIE2: Extended Interrupt Enable 2
Bit76543210
Name
ET5 ET4 ESMB1 ES1 EVBUS
Type R R R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b, Write = Don't Care.
5ET5
Enable Timer 5 Interrupt.
This bit sets the masking of the Timer 5 interrupt.
0: Disable Timer 5 interrupts.
1: Enable interrupt requests generated by the TF5L or TF5H flags.
4ET4
Enable Timer 4 Interrupt.
This bit sets the masking of the Timer 4 interrupt.
0: Disable Timer 4interrupts.
1: Enable interrupt requests generated by the TF4L or TF4H flags.
3 ESMB1
Enable SMBus1 Interrupt.
This bit sets the masking of the SMB1 interrupt.
0: Disable all SMB1 interrupts.
1: Enable interrupt requests generated by SMB1.
2 Reserved Must Write 0b.
1 ES1
Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt.
0 EVBUS
Enable VBUS Level Interrupt.
This bit sets the masking of the VBUS interrupt.
0: Disable all VBUS interrupts.
1: Enable interrupt requests generated by VBUS level sense.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 130
SFR Address = 0xF7; SFR Page = All Pages
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2
Bit76543210
Name
PT5 PT4 PSMB1 PS1 PVBUS
Type R R R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
:6 Unused Read = 00b, Write = Don't Care.
5PT5
Timer 5 Interrupt Priority Control.
This bit sets the priority of the Timer 5 interrupt.
0: Timer 5 interrupt set to low priority level.
1: Timer 5 interrupt set to high priority level.
4PT4
Timer 4 Interrupt Priority Control.
This bit sets the priority of the Timer 4 interrupt.
0: Timer 4 interrupt set to low priority level.
1: Timer 4 interrupt set to high priority level.
3 PSMB1
SMBus1 Interrupt Priority Control.
This bit sets the priority of the SMB1 interrupt.
0: SMB1 interrupt set to low priority level.
1: SMB1 interrupt set to high priority level.
2 Reserved Must Write 0b.
1 PS1
UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupt set to high priority level.
0 PVBUS
VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.
C8051F380/1/2/3/4/5/6/7/C
131 Rev. 1.5
16.3. INT0 and INT1 External Interrupt Sources
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0
Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “26.1. Timer 0 and Timer 1” on page 266) select level or
edge sensitive. The table below lists the possible configurations.
INT0
and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 16.7). Note
that INT0
and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0
and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register PnSKIP (see Section “20.1. Priority Crossbar
Decoder” on page 154 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0
and INT1 external inter-
rupts, respectively. If an INT0
or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
IT0 IN0PL INT0 Interrupt IT1 IN1PL INT1 Interrupt
1 0 Active low, edge sensitive 1 0 Active low, edge sensitive
1 1 Active high, edge sensitive 1 1 Active high, edge sensitive
0 0 Active low, level sensitive 0 0 Active low, level sensitive
0 1 Active high, level sensitive 0 1 Active high, level sensitive
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 132
SFR Address = 0xE4; SFR Page = 0
SFR Definition 16.7. IT01CF: INT0/INT1 ConfigurationO
Bit76543210
Name
IN1PL IN1SL[2:0] IN0PL IN0SL[2:0]
Type R/W R/W R/W R/W
Reset 00000001
Bit Name Function
7IN1PLINT1 Polarity.
0: INT1 input is active low.
1: INT1
input is active high.
6:4 IN1SL[2:0]
INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1
will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0
input is active high.
2:0 IN0SL[2:0]
INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0
will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
C8051F380/1/2/3/4/5/6/7/C
133 Rev. 1.5
17. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For V
DD
Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
Figure 17.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot)
(Software Reset)
System Reset
Reset
Funnel
Px.x
Px.x
EN
SWRSF
Internal
Oscillator
System
Clock
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
Clock Select
EN
WDT
Enable
MCD
Enable
XTAL1
External
Oscillator
Drive
Errant Flash
Operation
RST
(wired-OR)
Power On
Reset
0
+
-
Comparator 0
C0RSEF
VDD
+
-
Supply
Monitor
Enable
Low
Frequency
Oscillator
XTAL2
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 134
17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
DD
settles above
V
RST
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
ramp time
increases (V
DD
ramp time is defined as how fast V
DD
ramps from 0V to V
RST
). Figure 17.2. plots the
power-on and V
DD
monitor event timing. The maximum V
DD
ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before V
DD
reaches the V
RST
level. For ramp times less than
1 ms, the power-on reset delay (T
PORDelay
) is typically less than 0.3 ms.
On exit from a power-on or V
DD
monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V
DD
monitor
is enabled following a power-on reset.
Figure 17.2. Power-On and V
DD
Monitor Reset Timing
Power-On
Reset
VDD
Monitor
Reset
RST
t
Supply Voltage
Logic HIGH
Logic LOW
T
PORDelay
V
D
D
V
RST
VDD
C8051F380/1/2/3/4/5/6/7/C
135 Rev. 1.5
17.2. Power-Fail Reset / V
DD
Monitor
When a power-down transition or power irregularity causes V
DD
to drop below V
RST
, the power supply
monitor will drive the RST
pin low and hold the CIP-51 in a reset state (see Figure 17.2). When V
DD
returns
to a level above V
RST
, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if V
DD
dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
DD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
DD
monitor is disabled by code and a software reset is performed, the
V
DD
monitor will still be disabled after the reset.
I
mportant Note: If the V
DD
monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the V
DD
monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
DD
monitor and configuring it as a reset source from a disabled
state is shown below:
1. Enable the V
DD
monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the V
DD
monitor to stabilize (see Table 5.4 for the V
DD
Monitor turn-on time).
3. Select the V
DD
monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 17.2 for V
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
DD
monitor reset. See Table 5.4 for complete electrical characteristics of the V
DD
monitor.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 136
SFR Address = 0xFF; SFR Page = All Pages
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST
pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD time-out, a reset will be generated. After a MCD reset,
the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads
0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of
the RST
pin is unaffected by this reset.
17.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Com-
parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST
pin is unaffected by this reset.
SFR Definition 17.1. VDM0CN: V
DD
Monitor Control
Bit7654321 0
Name
VDMEN VDDSTAT
Type R/WRRRRRR R
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7VDMEN
V
DD
Monitor Enable.
This bit turns the V
DD
monitor circuit on/off. The V
DD
Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Defi-
nition 17.2). Selecting the V
DD
monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
DD
Monitor and selecting it as a
reset source. See Table 5.4 for the minimum V
DD
Monitor turn-on time.
0: V
DD
Monitor Disabled.
1: V
DD
Monitor Enabled.
6VDDSTAT
V
DD
Status.
This bit indicates the current power supply status (V
DD
Monitor output).
0: V
DD
is at or below the V
DD
monitor threshold.
1: V
DD
is above the V
DD
monitor threshold.
5:0 Unused Read = 000000b; Write = Don’t care.
C8051F380/1/2/3/4/5/6/7/C
137 Rev. 1.5
17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “27.4. Watchdog Timer Mode” on
page 308; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST
pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash program read, write, or erase operation targets an illegal address, a system reset is generated.
This may occur due to any of the following:
Programming hardware attempts to write or erase a Flash location which is above the user code space
address limit.
A Flash read from firmware is attempted above user code space. This occurs when a MOVC operation
is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
A Flash read, write, or erase attempt is restricted due to a Flash security setting.
A Flash write or erase is attempted when the V
DD
monitor is not enabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST
pin is unaffected by
this reset.
17.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST
pin is unaffected by this reset.
17.9. USB Reset
Writing 1 to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be
enabled for RESET signaling to be detected. See Section “21. Universal Serial Bus Controller (USB0)”
on page 172 for information on the USB Function Controller.
2. A falling or rising voltage on the VBUS pin.
The USBRSF bit will read 1 following a USB reset. The state of the RST
pin is unaffected by this reset.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 138
SFR Address = 0xEF; SFR Page = All Pages
SFR Definition 17.2. RSTSRC: Reset Source
Bit76543210
Name
USBRSF FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type R/W R R/W R/W R R/W R/W R
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Description Write Read
7 USBRSF USB Reset Flag Writing a 1 enables USB
as a reset source.
Set to 1 if USB caused the
last reset.
6FERROR
Flash Error Reset Flag. N/A Set to 1 if Flash
read/write/erase error
caused the last reset.
5 C0RSEF
Comparator0 Reset Enable
and Flag.
Writing a 1 enables Com-
parator0 as a reset source
(active-low).
Set to 1 if Comparator0
caused the last reset.
4SWRSF
Software Reset Force and
Flag.
Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
3 WDTRSF
Watchdog Timer Reset Flag. N/A Set to 1 if Watchdog Timer
overflow caused the last
reset.
2 MCDRSF
Missing Clock Detector
Enable and Flag.
Writing a 1 enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
1PORSF
Power-On / V
DD
Monitor
Reset Flag, and V
DD
monitor
Reset Enable.
Writing a 1 enables the
V
DD
monitor as a reset
source.
Writing 1 to this bit
before the V
DD
monitor
is enabled and stabilized
may cause a system
reset.
Set to 1 anytime a power-
on or V
DD
monitor reset
occurs.
When set to 1 all other
RSTSRC flags are inde-
terminate.
0PINRSFHW Pin Reset Flag. N/A Set to 1 if RST pin caused
the last reset.
Note: Do not use read-modify-write operations on this register
C8051F380/1/2/3/4/5/6/7/C
139 Rev. 1.5
18. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would
typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automat-
ically timed by hardware for proper execution; data polling to determine the end of the write/erase opera-
tion is not required. Code execution is stalled during a Flash write/erase operation.
18.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the C2 commands to program Flash memory, see Section “28. C2 Interface” on
page 316.
To ensure the integrity of Flash contents, it is strongly recommended that the V
DD
monitor be left enabled
in any system which writes or erases Flash memory from code. It is also crucial to ensure that the FLRT bit
in register FLSCL be set to '1' if a clock speed higher than 25 MHz is being used for the device.
18.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 18.2.
18.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by: (1) Writing the Flash key codes in sequence to the Flash Lock
register (FLKEY); and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this
directs the MOVX writes to target Flash memory). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash.
A byte location to be programmed must be erased before a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
1. Disable interrupts (recommended).
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSEE bit (register PSCTL).
5. Set the PSWE bit (register PSCTL).
6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
7. Clear the PSWE bit (register PSCTL).
8. Clear the PSEE bit (register PSCTI).
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 140
18.1.3. Flash Write Procedure
Bytes in Flash memory can be written one byte at a time, or in groups of two. The FLBWE bit in register
PFE0CN (SFR Definition ) controls whether a single byte or a block of two bytes is written to Flash during
a write operation. When FLBWE is cleared to 0, the Flash will be written one byte at a time. When FLBWE
is set to 1, the Flash will be written in two-byte blocks. Block writes are performed in the same amount of
time as single-byte writes, which can save time when storing large amounts of data to Flash mem-
ory.During a single-byte write to Flash, bytes are written individually, and a Flash write will be performed
after each MOVX write instruction. The recommended procedure for writing Flash in single bytes is:
1. Disable interrupts.
2. Clear the FLBWE bit (register PFE0CN) to select single-byte write mode.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
8. Clear the PSWE bit.
9. Re-enable interrupts.
Steps 5-7 must be repeated for each byte to be written.
For block Flash writes, the Flash write procedure is only performed after the last byte of each block is writ-
ten with the MOVX write instruction. A Flash write block is two bytes long, from even addresses to odd
addresses. Writes must be performed sequentially (i.e. addresses ending in 0b and 1b must be written in
order). The Flash write will be performed following the MOVX write that targets the address ending in 1b. If
a byte in the block does not need to be updated in Flash, it should be written to 0xFF. The recommended
procedure for writing Flash in blocks is:
1. Disable interrupts.
2. Set the FLBWE bit (register PFE0CN) to select block write mode.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write the first data byte to the even block location (ending in 0b).
8. Write the first key code to FLKEY: 0xA5.
9. Write the second key code to FLKEY: 0xF1.
10.Using the MOVX instruction, write the second data byte to the odd block location (ending in 1b).
11.Clear the PSWE bit.
12.Re-enable interrupts.
Steps 5–10 must be repeated for each block to be written.
C8051F380/1/2/3/4/5/6/7/C
141 Rev. 1.5
18.2. Non-Volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
18.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before soft-
ware can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock
n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where
n is the 1s complement number represented by the Security Lock Byte. Note that the page
containing the Flash Security Lock Byte is also locked when any other Flash pages are locked. See exam-
ple below.
Figure 18.1. Flash Program Memory Map and Security Byte
The level of FLASH security depends on the FLASH access method. The three FLASH access methods
that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing
on unlocked pages, and user firmware executing on locked pages.
Security Lock Byte: 11111101b
1s Complement: 00000010b
Flash pages locked: 3 (2 + Flash Lock Byte Page)
Addresses locked: First two pages of Flash: 0x0000 to 0x03FF
Flash Lock Byte Page: (0xFA00 to 0xFBFF for 64k devices; 0x7E00 to
0x7FFF for 32k devices, 0x3E00 to 0x3FFF for 16k devices)
Access limit set
according to the
FLASH security lock
byte
C8051F380/2/4/6
0x0000
0xFBFF
Lock Byte
Reserved
0xFC00
FLASH memory
organized in 512-byte
pages
Unlocked FLASH Pages
Locked when any
other FLASH pages
are locked
C8051F381/3/5/7
0x0000
0x7FFF
Lock Byte
0x7FFE
0x7E00
Unlocked FLASH Pages
C8051F38C
0x0000
Unlocked FLASH Pages
0x3FFE
0x3E00
0x3FFF
Lock Byte
0xFBFE
0xFA00
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 142
Accessing FLASH from the C2 debug interface:
1. Any unlocked page may be read, written, or erased.
2. Locked pages cannot be read, written, or erased.
3. The page containing the Lock Byte may be read, written, or erased if it is unlocked.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
6. Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) requires the C2 Device Erase command,
which erases all FLASH pages including the page containing the Lock Byte and the Lock Byte itself.
7. The Reserved Area cannot be read, written, or erased.
Accessing FLASH
from user firmware executing on an unlocked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Locked pages cannot be read, written, or erased.
3. The page containing the Lock Byte cannot be erased. It may be read or written only if it is unlocked.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
6. Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any
other locked page, will result in a FLASH Error device reset.
Accessing FLASH
from user firmware executing on a locked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Any locked page except the page containing the Lock Byte may be read, written, or erased.
3. The page containing the Lock Byte cannot be erased. It may only be read or written.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
6. Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any
other locked page, will result in a FLASH Error device reset.
C8051F380/1/2/3/4/5/6/7/C
143 Rev. 1.5
SFR Address =0x8F; SFR Page = All Pages
SFR Definition 18.1. PSCTL: Program Store R/W Control
Bit76543210
Name
PSEE PSWE
Type RRRRRRR/WR/W
Reset 00000000
Bit Name Function
7:2 Reserved Must write 000000b.
1 PSEE
Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0 PSWE
Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 144
SFR Address = 0xB7; SFR Page = All Pages
SFR Definition 18.2. FLKEY: Flash Lock and Key
Bit76543210
Name
FLKEY[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be perma-
nently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
C8051F380/1/2/3/4/5/6/7/C
145 Rev. 1.5
SFR Address = 0xB6; SFR Page = All Pages
SFR Definition 18.3. FLSCL: Flash Scale
Bit76543210
Name
FOSE Reserved FLRT Reserved
Type R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7FOSEFlash One-shot Enable.
This bit enables the Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads. At system
clock frequencies below 10 MHz, disabling the Flash one-shot will increase system
power consumption.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
6:5 Reserved Must write 00b.
4FLRT
FLASH Read Time.
This bit should be programmed to the smallest allowed value, according to the system
clock speed.
0: SYSCLK <= 25 MHz.
1: SYSCLK <= 48 MHz.
3:0 Reserved Must write 0000b.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 146
19. Oscillators and Clock Selection
C8051F380/1/2/3/4/5/6/7/C devices include a programmable internal high-frequency oscillator, a program-
mable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency
oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 19.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the
OSCLCN register. The system clock can be sourced by the external oscillator circuit or either internal oscil-
lator. Both internal oscillators offer a selectable post-scaling feature. The USB clock (USBCLK) can be
derived from the internal oscillators or external oscillator.
Figure 19.1. Oscillator Options
OSC
Programmable
Internal 48 MHz
Clock
Input
Circuit
EN
SYSCLK
OSCICL OSCICN
IOSCEN
IFRDY
SUSPEND
IFCN1
IFCN0
OSCXCN
XOSCMD2
XOSCMD1
XOSCMD0
XFCN2
XFCN1
XFCN0
CLKSEL
USBCLK2
USBCLK1
USBCLK0
CLKSL2
CLKSL1
CLKSL0
OSCLCN
OSCLEN
OSCLRDY
OSCLF3
OSCLF2
OSCLF1
OSCLF0
OSCLD1
OSCLD0
80 kHz Low
Frequency Oscillator
EN
1, 2, 4, 8
OSCLD
OSCLF
OSCLF OSCLD
USBCLK
CLKMUL
MULEN
MULINT
MULRDY
MULSEL1
MULSEL0
USBCLK2-0
Internal HFO / 8
EXOSC
EXOSC / 2
EXOSC / 3
EXOSC / 4
Internal LFO
Internal HFO
OSCLEN
OSCLEN
XTAL1
XTAL2
Option 2
VDD
XTAL2
Option 1
10M
Option 3
XTAL2
Option 4
XTAL2
1, 2, 4, 82 2
(12 MHz)
(24 MHz)
(48 MHz)
C8051F380/1/2/3/4/5/6/7/C
147 Rev. 1.5
19.1. System Clock Selection
The CLKSL[2:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[2:0] must be set to 001b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillators and external
oscillator so long as the selected clock source is enabled and running.
The internal high-frequency and low-frequency oscillators require little start-up time and may be selected
as the system clock immediately following the register write which enables the oscillator. The external RC
and C modes also typically require no startup time.
19.2. USB Clock Selection
The USBCLK[2:0] bits in register CLKSEL select which oscillator source is used as the USB clock. The
USB clock may be derived from the internal oscillators, a divided version of the internal High-Frequency
oscillator, or a divided version of the external oscillator. Note that the USB clock must be 48 MHz when
operating USB0 as a Full Speed Function; the USB clock must be 6 MHz when operating USB0 as a Low
Speed Function. See SFR Definition 19.1 for USB clock selection options.
Some example USB clock configurations for Full and Low Speed mode are given below:
USB Full Speed (48 MHz)
Internal Oscillator
Clock Signal Input Source Selection Register Bit Settings
USB Clock Internal Oscillator* USBCLK = 000b
Internal Oscillator Divide by 1 IFCN = 11b
External Oscillator
Clock Signal Input Source Selection Register Bit Settings
USB Clock External Oscillator USBCLK = 010b
External Oscillator CMOS Oscillator Mode
48 MHz Oscillator
XOSCMD = 010b
Note: Clock Recovery must be enabled for this configuration.
USB Low Speed (6 MHz)
Internal Oscillator
Clock Signal Input Source Selection Register Bit Settings
USB Clock Internal Oscillator / 8 USBCLK = 001b
Internal Oscillator Divide by 1 IFCN = 11b
External Oscillator
Clock Signal Input Source Selection Register Bit Settings
USB Clock External Oscillator / 4 USBCLK = 101b
External Oscillator CMOS Oscillator Mode
24 MHz Oscillator
XOSCMD = 010b
Crystal Oscillator Mode
24 MHz Oscillator
XOSCMD = 110b
XFCN = 111b
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 148
SFR Address = 0xA9; SFR Page = All Pages
SFR Definition 19.1. CLKSEL: Clock Select
Bit76543210
Name
USBCLK[2:0] OUTCLK CLKSL[2:0]
Type R R/W R/W R/W
Reset 00000000
Bit Name Function
7 Unused Read = 0b; Write = don’t care
6:4 USBCLK[2:0]
USB Clock Source Select Bits.
000: USBCLK derived from the Internal High-Frequency Oscillator.
001: USBCLK derived from the Internal High-Frequency Oscillator / 8.
010: USBCLK derived from the External Oscillator.
011: USBCLK derived from the External Oscillator/2.
100: USBCLK derived from the External Oscillator/3.
101: USBCLK derived from the External Oscillator/4.
110: USBCLK derived from the Internal Low-Frequency Oscillator.
111: Reserved.
3 OUTCLK
Crossbar Clock Out Select.
If the SYSCLK signal is enabled on the Crossbar, this bit selects between outputting
SYSCLK and SYSCLK synchronized with the Port I/O pins.
0: Enabling the Crossbar SYSCLK
signal outputs SYSCLK.
1: Enabling the Crossbar SYSCLK
signal outputs SYSCLK synchronized with the
Port I/O.
2:0 CLKSL[2:0]
System Clock Source Select Bits.
000: SYSCLK derived from the Internal High-Frequency Oscillator / 4 and scaled
per the IFCN bits in register OSCICN.
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the Internal High-Frequency Oscillator / 2.
011: SYSCLK derived from the Internal High-Frequency Oscillator.
100: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per
the OSCLD bits in register OSCLCN.
101-111: Reserved.
C8051F380/1/2/3/4/5/6/7/C
149 Rev. 1.5
19.3. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F380/1/2/3/4/5/6/7/C devices include a programmable internal high-frequency oscillator that
defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the
OSCICL register as defined by SFR Definition 19.2.
On C8051F380/1/2/3/4/5/6/7/C devices, OSCICL is factory calibrated to obtain a 48 MHz base frequency.
Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8
after a divide by 4 stage, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 fol-
lowing a reset, which results in a 1.5 MHz system clock.
19.3.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until a non-idle USB event is detected or a rising or falling edge occurs on the VBUS signal. Note that the
USB transceiver can still detect USB events when it is disabled.
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation. The CPU resumes execution at the instruction following the write to the SUS-
PEND bit.
Note: The prefetch engine can be turned off in suspend mode to save power. Additionally, both Voltage
Regulators (REG0 and REG1) have low-power modes for additional power savings in suspend mode.
SFR Address = 0xB3; SFR Page = All Pages
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration
Bit76543210
Name
OSCICL[6:0]
Type RR/W
Reset 0 Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7 Unused Read = 0; Write = don’t care
6:0 OSCICL[6:0]
Internal Oscillator Calibration Bits.
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 48 MHz. OSCICL should only be changed by firm-
ware when the H-F oscillator is disabled (IOSCEN = 0).
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 150
SFR Address = 0xB2; SFR Page = All Pages
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control
Bit76 5 43210
Name
IOSCEN IFRDY SUSPEND IFCN[1:0]
Type R/W R R/W R R R R/W
Reset 11 0 00000
Bit Name Function
7IOSCENInternal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6IFRDY
Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
5 SUSPEND
Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4:2 Unused Read = 000b; Write = don’t care
1:0 IFCN[1:0]
Internal H-F Oscillator Frequency Divider Control Bits.
The Internal H-F Oscillator is divided by the IFCN bit setting after a divide-by-4 stage.
00: SYSCLK can be derived from Internal H-F Oscillator divided by 8 (1.5 MHz).
01: SYSCLK can be derived from Internal H-F Oscillator divided by 4 (3 MHz).
10: SYSCLK can be derived from Internal H-F Oscillator divided by 2 (6 MHz).
11: SYSCLK can be derived from Internal H-F Oscillator divided by 1 (12 MHz).
C8051F380/1/2/3/4/5/6/7/C
151 Rev. 1.5
19.4. Clock Multiplier
The C8051F380/1/2/3/4/5/6/7/C device includes a 48 MHz high-frequency oscillator instead of a 12 MHz
oscillator and a 4x Clock Multiplier, so the USB0 module can be run directly from the internal high-fre-
quency oscillator. For compatibility with C8051F34x and C8051F32x devices however, the CLKMUL regis-
ter (SFR Definition 19.4) behaves as if the Clock Multiplier is present and working.
SFR Address = 0xB9; SFR Page = 0
SFR Definition 19.4. CLKMUL: Clock Multiplier Control
Bit76543210
Name
MULEN MULINIT MULRDY MULSEL[1:0]
Type RRRRRR R
Reset 11100000
Bit Name Description
7MULENClock Multiplier Enable Bit.
This bit always reads 1.
6MULINIT
Clock Multiplier Initialize Bit.
This bit always reads 1.
5 MULRDY
Clock Multiplier Ready Bit.
This bit always reads 1.
4:2 Unused Read = 000b; Write = don’t care
1:0 MULSEL[1:0]
Clock Multiplier Input Select Bits.
These bits always read 00.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 152
19.5. Programmable Internal Low-Frequency (L-F) Oscillator
All C8051F380/1/2/3/4/5/6/7/C devices include a programmable low-frequency internal oscillator, which is
calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can
be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR
Definition 19.5). Additionally, the OSCLF[3:0] bits can be used to adjust the oscillator’s output frequency.
19.5.1. Calibrating the Internal L-F Oscillator
Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when run-
ning from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture
Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a
capture event on the corresponding timer. As a capture event occurs, the current timer value
(TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the differ-
ence between two successive timer capture values, the low-frequency oscillator’s period can be calcu-
lated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency.
SFR Address = 0x86; SFR Page = All Pages
SFR Definition 19.5. OSCLCN: Internal L-F Oscillator Control
Bit76543210
Name
OSCLEN OSCLRDY OSCLF[3:0] OSCLD[1:0]
Type R/W R R.W R/W
Reset 0 0 Varies Varies Varies Varies 0 0
Bit Name Function
7OSCLENInternal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
6OSCLRDY
Internal L-F Oscillator Ready.
0: Internal L-F Oscillator frequency not stabilized.
1: Internal L-F Oscillator frequency stabilized.
Note: OSCLRDY is only set back to 0 in the event of a device reset or a change to the
OSCLD[1:0] bits.
5:2 OSCLF[3:0] Internal L-F Oscillator Frequency Control Bits.
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the
L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator
operates at its slowest setting. The OSCLF bits should only be changed by firmware
when the L-F oscillator is disabled (OSCLEN = 0).
1:0 OSCLD[1:0]
Internal L-F Oscillator Divider Select.
00: Divide by 8 selected.
01: Divide by 4 selected.
10: Divide by 2 selected.
11: Divide by 1 selected.
C8051F380/1/2/3/4/5/6/7/C
153 Rev. 1.5
19.6. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. Figure 19.1 shows a block diagram of the four external oscil-
lator options. The external oscillator is enabled and configured using the OSCXCN register (see SFR Defi-
nition 19.6).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2, respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pin used by the oscillator circuit; see Section “20.1. Priority Crossbar
Decoder” on page 154 for Crossbar configuration. Additionally, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as
analog inputs.
In CMOS clock mode, the associated pin should be configured as a
digital input. See Section “20.2. Port
I/O Initialization” on page 158 for details on Port input mode selection.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g. Timers, PCA, etc.). See the data sheet chapters for each digital peripheral for details. See
Section “5. Electrical Characteristics” on page 41 for complete oscillator specifications.
19.6.1. External Crystal Mode
If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 Mresis-
tor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 19.1, “Crystal Mode”. Appropriate
loading capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog
I/O with the digital output drivers disabled.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The recommended load capacitance depends upon the crystal and the manufacturer. Refer to the
crystal data sheet when completing these calculations.
The equation for determining the load capacitance for two capacitors is
Where:
C
A
and C
B
are the capacitors connected to the crystal leads.
C
S
is the total stray capacitance of the PCB.
The stray capacitance for a typical layout where the crystal is as close as possible to the pins is 2-5 pF per
pin.
If C
A
and C
B
are the same (C), then the equation becomes
For example, a tuning-fork crystal of 32 kHz with a recommended load capacitance of 12.5 pF should use
the configuration shown in Figure 19.1, Option 1. With a stray capacitance of 3 pF per pin (6 pF total), the
13 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 19.2.
C
L
C
A
C
B
C
A
C
B
+
----------------------- C
S
+=
C
L
C
2
----C
S
+=
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 154
Figure 19.2. External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for
Crystal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures
that the clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Fre-
quency Control value (XFCN) must also be specified based on the crystal frequency (see SFR Definition
19.6).
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to deter-
mine when the external system clock is valid and running. Switching to the external oscillator before the
crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure for start-
ing the crystal is:
1. Configure XTAL1 and XTAL2 for analog I/O.
2. Disable the XTAL1 and XTAL2 digital output drivers by writing 1s to the appropriate bits in the Port
Latch register.
3. Configure and enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD >
1.
6. Switch the system clock to the external oscillator.
13 pF
13 pF
32 kHz
XTAL1
XTAL2
10 M
C8051F380/1/2/3/4/5/6/7/C
155 Rev. 1.5
19.6.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 19.1, “RC Mode”. The capacitor should be no greater than 100 pF; however, for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter-
mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation , where
f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor value in
k
.
Equation 19.1. RC Mode Oscillator Frequency
For example: If the frequency desired is 100 kHz, let R = 246 k and C = 50 pF:
f = 1.23( 10
3
) / RC = 1.23 ( 10
3
) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 19.6, the required XFCN setting is 010b.
19.6.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 19.1, “C Mode”. The capacitor should be no greater than 100 pF; however, for very small capaci-
tors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci-
tor to be used and find the frequency of oscillation according to Equation , where f = the frequency of oscil-
lation in MHz, C = the capacitor value in pF, and V
DD
= the MCU power supply in Volts.
Equation 19.2. C Mode Oscillator Frequency
For example: Assume V
DD
= 3.0 V and f = 150 kHz:
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 19.6
(OSCXCN) as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
f1.2310
3
RC§=
fKFCV
DD
=
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 156
SFR Address = 0xB1; SFR Page = All Pages
SFR Definition 19.6. OSCXCN: External Oscillator Control
Bit76543210
Name
XCLKVLD XOSCMD[2:0] XFCN[2:0]
Type RR/WRR/W
Reset 00000000
Bit Name Function
7 XCLKVLD External Oscillator Valid Flag.
Provides External Oscillator status and is valid at all times for all modes of opera-
tion except External CMOS Clock Mode and External CMOS Clock Mode with
divide by 2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
6:4 XOSCMD[2:0]
External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide-by-2 stage.
100: RC Oscillator Mode with divide-by-2 stage.
101: Capacitor Oscillator Mode with divide-by-2 stage.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide-by-2 stage.
3 Unused Read = 0; Write = don’t care
2:0 XFCN[2:0]
External Oscillator Frequency Control Bits.
Set according to the desired frequency for RC mode.
Set according to the desired K Factor for C mode.
XFCN Crystal Mode RC Mode C Mode
000 f 20 kHz f 25 kHz K Factor = 0.87
001 20 kHz
f 58 kHz 25 kHz f 50 kHz K Factor = 2.6
010 58 kHz
f 155 kHz 50 kHz f 100 kHz K Factor = 7.7
011 155 kHz
f 415 kHz 100 kHz f 200 kHz K Factor = 22
100 415 kHz
f 1.1 MHz 200 kHz f 400 kHz K Factor = 65
101 1.1 MHz
f 3.1 MHz 400 kHz f 800 kHz K Factor = 180
110 3.1 MHz
f 8.2 MHz 800 kHz f 1.6 MHz K Factor = 664
111 8.2 MHz
f 25 MHz 1.6 MHz f 3.2 MHz K Factor = 1590
C8051F380/1/2/3/4/5/6/7/C
157 Rev. 1.5
20. Port Input/Output
Digital and analog resources are available through 40 I/O pins (C8051F380/2/4/6) or 25 I/O pins
(C8051F381/3/5/7/C). Port pins are organized as shown in Figure 20.1. Each of the Port pins can be
defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the
internal digital resources as shown in Figure 20.3. The designer has complete control over which functions
are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is
achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always
be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 20.1, SFR
Definition 20.2, and SFR Definition 20.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4).
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
XBR0, XBR1, XBR2,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
PnMDOUT,
PnMDIN Registers
UART0
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus0
T0, T1
2
6
PCA
CP1
Outputs
2
4
SPI
CP0
Outputs
2
P1
I/O
Cells
P1.0
P1.7
8
P2
I/O
Cells
P2.0
P2.7
8
P3
I/O
Cells
P3.0
8
(Port Latches)
P0
8
8
8
8
P1
P2
P3
*P3.1-P3.7 only available on 48-pin
packages
UART1
2
P3.7*
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7*)
2
SMBus1
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 158
Figure 20.2. Port I/O Cell Block Diagram
20.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 20.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be
set. This applies to the VREF signal, external oscillator pins (XTAL1, XTAL2), the ADC’s external conver-
sion start signal (CNVSTR), EMIF control signals, and any selected ADC or Comparator inputs. The
PnSKIP registers may also be used to skip pins to be used as GPIO. The Crossbar skips selected pins as
if they were already assigned, and moves to the next unassigned pin. Figure 20.3 shows all the possible
pins available to each peripheral. Figure 20.4 shows an example Crossbar configuration with no Port pins
skipped. Figure 20.5 shows the same Crossbar example with pins P0.2, P0.3, and P1.0 skipped.
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when either SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the priori-
tized functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
GND
PORT-OUTENABLE
PORT-OUTPUT
PUSH-PULL
VDD
VDD
WEAK-PULLUP
(WEAK)
PORT
PAD
ANALOG INPUT
Analog Select
PORT-INPUT
C8051F380/1/2/3/4/5/6/7/C
159 Rev. 1.5
Figure 20.3. Peripheral Availability on Port I/O Pins
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
P0
SF Signals
(48-pin
Package)
0 0 0 0 0 0 0 0
P0SKIP
Pin Skip
Settings
CP1
CP1A
SCK
MISO
MOSI
NSS*
CEX3
CEX4
P1
0 0 0 0 0 0 0 0
P1SKIP
P2
0 0 0 0 0 0 0 0
P2SKIP
P3
0 0 0 0 0 0 0 0
P3SKIP
The crossbar peripherals are assigned in priority order from top to bottom, according to this diagram.
These boxes represent Port pins which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are enabled, the Crossbar should be
manually configured to skip the corresponding port pins.
Pins can be “skipped” by setting the corresponding bit in PnSKIP to 1.
* NSS is only pinned out when the SPI is in 4-wire mode.
TX1
RX1
SDA1
SCL1
SF Signals
(32-pin
Package)
XTAL1
XTAL2
CNVSTR
VREF
P3.1-P3.7
Unavailable on 32-pin
packages
XTAL1
XTAL2
ALE
CNVSTR
VREF
/RD
/WR
0 1 2 3 4 5 6 7Pin Number 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Port
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 160
Figure 20.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped)
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0 1 2 3 4 5 6 7
P0Port
Pin Number
48-pin
Special
Function
Signals
XTAL1
0 0 0 0 0 0 0 0
P0SKIP
Pin Skip
Settings
XTAL2
CP1
CP1A
SCK
MISO
MOSI
NSS*
CEX3
CEX4
0 1 2 3 4 5 6 7
P1
ALE
RD
0 0 0 0 0 0 0 0
P1SKIP
CNVSTR
VREF
WR
0 1 2 3 4 5 6 7
P2
0 0 0 0 0 0 0 0
P2SKIP
0 1 2 3 4 5 6 7
P3
0 0 0 0 0 0 0 0
P3SKIP
This example shows a crossbar configuration with XBR0 = 0x07 and XBR1 = 0x43.
These boxes represent Port pins which are assigned to a peripheral.
TX1
RX1
SDA1
SCL1
32-pin
Special
Function
Signals
XTAL2
CNVSTR
XTAL1
VREF
Unavailable on 32-pin
packages
TX0 and RX0 are fixed at these locations
The other peripherals are assigned based on pin
availability, in priority order.
C8051F380/1/2/3/4/5/6/7/C
161 Rev. 1.5
Figure 20.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0 1 2 3 4 5 6 7
P0Port
Pin Number
48-pin
Special
Function
Signals
XTAL1
0 0 1 1 0 0 0 0
P0SKIP
Pin Skip
Settings
XTAL2
CP1
CP1A
SCK
MISO
MOSI
NSS*
CEX3
CEX4
0 1 2 3 4 5 6 7
P1
ALE
RD
1 0 0 0 0 0 0 0
P1SKIP
CNVSTR
VREF
WR
0 1 2 3 4 5 6 7
P2
0 0 0 0 0 0 0 0
P2SKIP
0 1 2 3 4 5 6 7
P3
0 0 0 0 0 0 0 0
P3SKIP
This example shows a crossbar configuration with XBR0 = 0x07 and XBR1 = 0x43.
These boxes represent Port pins which are assigned to a peripheral.
TX1
RX1
SDA1
SCL1
32-pin
Special
Function
Signals
XTAL2
CNVSTR
XTAL1
VREF
Unavailable on 32-pin
packages
P0.2 Skipped
P0.3 Skipped
P1.0 Skipped
If a pin is skipped, it is not available for assignment, and the
crossbar will move the assignment to the next available pin
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 162
20.2. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals (XBR0, XBR1).
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this
practice is not recommended. To configure a Port pin for digital input, write 0 to the corresponding bit in
register PnMDOUT, and write 1 to the corresponding Port latch (register Pn).
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates
a digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this are the SMBus (SDA, SCL, SDA1 and SCL1) pins, which are configured as open-drain
regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is 0, a weak pull-up is enabled for
all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the
weak pull-up is turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the
Port I/O pin-assignments based on the XBRn Register settings.
Important Note: The Crossbar must be enabled to use Ports P0, P1, P2, and P3 as standard Port I/O in
output mode. These Port output drivers are disabled while the Crossbar is disabled. Port 4 always func-
tions as standard GPIO.
C8051F380/1/2/3/4/5/6/7/C
163 Rev. 1.5
SFR Address = 0xE1; SFR Page = All Pages
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0
Bit76543210
Name
CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP1AEComparator1 Asynchronous Output Enable.
0: Asynchronous CP1A unavailable at Port pin.
1: Asynchronous CP1A routed to Port pin.
6CP1E
Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
5CP0AE
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0A unavailable at Port pin.
1: Asynchronous CP0A routed to Port pin.
4CP0E
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
3 SYSCKE
SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK
output routed to Port pin.
2SMB0E
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
1SPI0E
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0URT0E
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 164
SFR Address = 0xE2; SFR Page = All Pages
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1
Bit7 6543210
Name
WEAKPUD XBARE T1E T0E ECIE PCA0ME[2:0]
Type R/W R/WR/WR/WR/WR/WR/WR/W
Reset 0 0000000
Bit Name Function
7 WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6 XBARE
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5T1E
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
4T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
3ECIE
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
2:0 PCA0ME[2:0]
PCA Module I/O Enable Bits.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
11x: Reserved.
C8051F380/1/2/3/4/5/6/7/C
165 Rev. 1.5
SFR Address = 0xE3; SFR Page = All Pages
20.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that
are both byte addressable and bit addressable. Port 4 (C8051F380/2/4/6 only) uses an SFR which is
byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output
data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the
XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can
always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write
instructions. The read-modify-write instructions when operating on a Port SFR are the following: ANL,
ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit
in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written
back to the SFR.
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2
Bit7 6543210
Name
SMB1E URT1E
Type R/W R/WR/WR/WR/WR/WR/WR/W
Reset 0 0000000
Bit Name Function
7:2 Reserved Must write 000000b
1SMB1E
SMBus1 I/O Enable.
0: SMBus1 I/O unavailable at Port pins.
1: SMBus1 I/O routed to Port pins.
0URT1E
UART1 I/OEnable.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX1, RX1 routed to Port pins.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 166
SFR Address = 0x80; SFR Page = All Pages; Bit Addressable
SFR Address = 0xF1; SFR Page = All Pages
SFR Definition 20.4. P0: Port 0
Bit76543210
Name
P0[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P0[7:0] Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 20.5. P0MDIN: Port 0 Input Mode
Bit76543210
Name
P0MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
C8051F380/1/2/3/4/5/6/7/C
167 Rev. 1.5
SFR Address = 0xA4; SFR Page = All Pages
SFR Address = 0xD4; SFR Page = All Pages
SFR Definition 20.6. P0MDOUT: Port 0 Output Mode
Bit76543210
Name
P0MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
SFR Definition 20.7. P0SKIP: Port 0 Skip
Bit76543210
Name
P0SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 168
SFR Address = 0x90; SFR Page = All Pages; Bit Addressable
SFR Address = 0xF2; SFR Page = All Pages
SFR Definition 20.8. P1: Port 1
Bit76543210
Name
P1[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P1[7:0] Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
SFR Definition 20.9. P1MDIN: Port 1 Input Mode
Bit76543210
Name
P1MDIN[7:0]
Type R/W
Reset 1*1111111
Bit Name Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
C8051F380/1/2/3/4/5/6/7/C
169 Rev. 1.5
SFR Address = 0xA5; SFR Page = All Pages
SFR Address = 0xD5; SFR Page = All Pages
SFR Definition 20.10. P1MDOUT: Port 1 Output Mode
Bit76543210
Name
P1MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
SFR Definition 20.11. P1SKIP: Port 1 Skip
Bit76543210
Name
P1SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 170
SFR Address = 0xA0; SFR Page = All Pages; Bit Addressable
SFR Address = 0xF3; SFR Page = All Pages
SFR Definition 20.12. P2: Port 2
Bit76543210
Name
P2[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P2[7:0] Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
SFR Definition 20.13. P2MDIN: Port 2 Input Mode
Bit76543210
Name
P2MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
C8051F380/1/2/3/4/5/6/7/C
171 Rev. 1.5
SFR Address = 0xA6; SFR Page = All Pages
SFR Address = 0xD6; SFR Page = All Pages
SFR Definition 20.14. P2MDOUT: Port 2 Output Mode
Bit76543210
Name
P2MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
SFR Definition 20.15. P2SKIP: Port 2 Skip
Bit76543210
Name
P2SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2SKIP[3:0] Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 172
SFR Address = 0xB0; SFR Page = All Pages; Bit Addressable
SFR Address = 0xF4; SFR Page = All Pages
SFR Definition 20.16. P3: Port 3
Bit76543210
Name
P3[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P3[7:0] Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
SFR Definition 20.17. P3MDIN: Port 3 Input Mode
Bit76543210
Name
P3MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P3MDIN[7:0] Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
C8051F380/1/2/3/4/5/6/7/C
173 Rev. 1.5
SFR Address = 0xA7; SFR Page = All Pages
SFR Address = 0xDF; SFR Page = All Pages
SFR Definition 20.18. P3MDOUT: Port 3 Output Mode
Bit76543210
Name
P3MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P3MDOUT[7:0] Output Configuration Bits for P3.7–P3.0 (respectively).
These bits are ignored if the corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
SFR Definition 20.19. P3SKIP: Port 3 Skip
Bit76543210
Name
P3SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P3SKIP[3:0] Port 3 Crossbar Skip Enable Bits.
These bits select Port 3 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P3.n pin is not skipped by the Crossbar.
1: Corresponding P3.n pin is skipped by the Crossbar.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 174
SFR Address = 0xC7; SFR Page = All Pages
SFR Address = 0xF5; SFR Page = All Pages
SFR Definition 20.20. P4: Port 4
Bit76543210
Name
P4[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P4[7:0] Port 4 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P4.n Port pin is logic
LOW.
1: P4.n Port pin is logic
HIGH.
SFR Definition 20.21. P4MDIN: Port 4 Input Mode
Bit76543210
Name
P4MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P4MDIN[7:0] Analog Configuration Bits for P4.7–P4.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P4.n pin is configured for analog mode.
1: Corresponding P4.n pin is not configured for analog mode.
C8051F380/1/2/3/4/5/6/7/C
175 Rev. 1.5
SFR Address = 0xAE; SFR Page = All Pages
SFR Definition 20.22. P4MDOUT: Port 4 Output Mode
Bit76543210
Name
P4MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P4MDOUT[7:0] Output Configuration Bits for P4.7–P4.0 (respectively).
These bits are ignored if the corresponding bit in register P4MDIN is logic 0.
0: Corresponding P4.n Output is open-drain.
1: Corresponding P4.n Output is push-pull.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 176
21. Universal Serial Bus Controller (USB0)
C8051F380/1/2/3/4/5/6/7/C devices include a complete Full/Low Speed USB function for USB peripheral
implementations. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB
Transceiver (including matching resistors and configurable pull-up resistors), 1 kB FIFO block, and clock
recovery mechanism for crystal-less operation. No external components are required. The USB Function
Controller and Transceiver is Universal Serial Bus Specification 2.0 compliant.
Figure 21.1. USB0 Block Diagram
Important Note: This document assumes a comprehensive understanding of the USB Protocol. Terms and
abbreviations used in this document are defined in the USB Specification. We encourage you to review the
latest version of the USB Specification before proceeding.
Note: The C8051F380/1/2/3/4/5/6/7/C cannot be used as a USB Host device.
21.1. Endpoint Addressing
A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-
directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint
pipes:
Transceiver Serial Interface Engine (SIE)
USB FIFOs
(1k RAM)
D+
D-
VDD
Endpoint0
IN/OUT
Endpoint1
IN OUT
Endpoint2
IN OUT
Endpoint3
IN OUT
Data
Transfer
Control
CIP-51 Core
USB
Control,
Status, and
Interrupt
Registers
C8051F380/1/2/3/4/5/6/7/C
177 Rev. 1.5
21.2. USB Transceiver
The USB Transceiver is configured via the USB0XCN register shown in SFR Definition 21.1. This configu-
ration includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection
(Full or Low Speed). When bit SPEED = 1, USB0 operates as a Full Speed USB function, and the on-chip
pull-up resistor (if enabled) appears on the D+ pin. When bit SPEED = 0, USB0 operates as a Low Speed
USB function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register
USB0XCN can be used for Transceiver testing as described in SFR Definition 21.1. The pull-up resistor is
enabled only when VBUS is present (see Section “9.1.2. VBUS Detection” on page 78 for details on VBUS
detection).
Important Note: The USB clock should be active before the Transceiver is enabled.
Table 21.1. Endpoint Addressing Scheme
Endpoint Associated Pipes USB Protocol Address
Endpoint0 Endpoint0 IN 0x00
Endpoint0 OUT 0x00
Endpoint1 Endpoint1 IN 0x81
Endpoint1 OUT 0x01
Endpoint2 Endpoint2 IN 0x82
Endpoint2 OUT 0x02
Endpoint3 Endpoint3 IN 0x83
Endpoint3 OUT 0x03
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 178
SFR Address = 0xD7; SFR Page = All Pages
SFR Definition 21.1. USB0XCN: USB0 Transceiver Control
Bit76543210
Name
PREN PHYEN SPEED PHYTST[1:0] DFREC Dp Dn
Type R/W R/W R/W R/W R R R
Reset 00000000
Bit Name Function
7PRENInternal Pull-up Resistor Enable.
The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit.
0: Internal pull-up resistor disabled (device effectively detached from USB network).
1: Internal pull-up resistor enabled when VBUS is present (device attached to the
USB network).
6 PHYEN
Physical Layer Enable.
0: USB0 physical layer Transceiver disabled (suspend).
1: USB0 physical layer Transceiver enabled (normal).
5 SPEED
USB0 Speed Select.
This bit selects the USB0 speed.
0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor
appears on the D– line.
1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor
appears on the D+ line.
4:3 PHYTST[1:0]
Physical Layer Test Bits.
00: Mode 0: Normal (non-test mode) (D+ = X, D- = X)
01: Mode 1: Differential 1 Forced (D+ = 1, D- = 0)
10: Mode 2: Differential 0 Forced (D+ = 0, D- = 1)
11: Mode 3: Single-Ended 0 Forced (D+ = 0, D– = 0)
2DFREC
Differential Receiver Bit
The state of this bit indicates the current differential value present on the D+ and D-
lines when PHYEN = 1.
0: Differential 0 signalling on the bus.
1: Differential 1 signalling on the bus.
1Dp
D+ Signal Status.
This bit indicates the current logic level of the D+ pin.
0: D+ signal currently at logic 0.
1: D+ signal currently at logic 1.
0Dn
D- Signal Status.
This bit indicates the current logic level of the D- pin.
0: D- signal currently at logic 0.
1: D- signal currently at logic 1.
C8051F380/1/2/3/4/5/6/7/C
179 Rev. 1.5
21.3. USB Register Access
The USB0 controller registers listed in Table 21.2 are accessed through two SFRs: USB0 Address
(USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted
by reads/writes of the USB0DAT register. See Figure 21.2.
Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end-
point number. Once the target endpoint number is written to the INDEX register, the control/status registers
associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 21.2
for a list of endpoint control/status registers.
Important Note: The USB clock must be active when accessing USB registers.
Figure 21.2. USB0 Register Access Scheme
USB Controller
FIFO
Access
Index
Register
Endpoint0 Control/
Status Registers
Endpoint1 Control/
Status Registers
Endpoint2 Control/
Status Registers
Endpoint3 Control/
Status Registers
Common
Registers
Interrupt
Registers
8051
SFRs
USB0ADR
USB0DAT
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 180
SFR Address = 0x96; SFR Page = All Pages
SFR Definition 21.2. USB0ADR: USB0 Indirect Address
Bit76543210
Name
BUSY AUTORD USBADDR[5:0]
Type R/W R/W R/W
Reset 00000000
Bit Name Description Write Read
7BUSYUSB0 Register Read
Busy Flag.
This bit is used during
indirect USB0 register
accesses.
0: No effect.
1: A USB0 indirect regis-
ter read is initiated at the
address specified by the
USBADDR bits.
0: USB0DAT register data
is valid.
1: USB0 is busy access-
ing an indirect register;
USB0DAT register data is
invalid.
6AUTORD
USB0 Register Auto-read Flag.
This bit is used for block FIFO reads.
0: BUSY must be written manually for each USB0 indirect register read.
1: The next indirect register read will automatically be initiated when software
reads USB0DAT (USBADDR bits will not be changed).
5:0 USBADDR[5:0]
USB0 Indirect Register Address Bits.
These bits hold a 6-bit address used to indirectly access the USB0 core registers.
Table 21.2 lists the USB0 core registers and their indirect addresses. Reads and
writes to USB0DAT will target the register indicated by the USBADDR bits.
C8051F380/1/2/3/4/5/6/7/C
181 Rev. 1.5
SFR Address = 0x97; SFR Page = All Pages
SFR Definition 21.3. USB0DAT: USB0 Data
Bit76543210
Name
USB0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Description Write Read
7:0 USB0DAT[7:0] USB0 Data Bits.
This SFR is used to indi-
rectly read and write
USB0 registers.
Write Procedure:
1. Poll for BUSY
(USB0ADR.7) => 0.
2. Load the target USB0
register address into the
USBADDR bits in register
USB0ADR.
3. Write data to USB0DAT.
4. Repeat (Step 2 may be
skipped when writing to
the same USB0 register).
Read Procedure:
1. Poll for BUSY
(USB0ADR.7) => 0.
2. Load the target USB0
register address into the
USBADDR bits in register
USB0ADR.
3. Write 1 to the BUSY bit
in register USB0ADR
(steps 2 and 3 can be per-
formed in the same write).
4. Poll for BUSY
(USB0ADR.7) => 0.
5. Read data from USB0-
DAT.
6. Repeat from Step 2
(Step 2 may be skipped
when reading the same
USB0 register; Step 3 may
be skipped when the
AUTORD bit
(USB0ADR.6) is logic 1).
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 182
Table 21.2. USB0 Controller Registers
USB Register
Name
USB Register
Address
Description Page Number
Interrupt Registers
IN1INT 0x02 Endpoint0 and Endpoints1-3 IN Interrupt Flags 191
OUT1INT 0x04 Endpoints1-3 OUT Interrupt Flags 192
CMINT 0x06 Common USB Interrupt Flags 193
IN1IE 0x07 Endpoint0 and Endpoints1-3 IN Interrupt Enables 194
OUT1IE 0x09 Endpoints1-3 OUT Interrupt Enables 195
CMIE 0x0B Common USB Interrupt Enables 196
Common Registers
FADDR 0x00 Function Address 187
POWER 0x01 Power Management 189
FRAMEL 0x0C Frame Number Low Byte 190
FRAMEH 0x0D Frame Number High Byte 190
INDEX 0x0E Endpoint Index Selection 183
CLKREC 0x0F Clock Recovery Control 184
EENABLE 0x1E Endpoint Enable 201
FIFOn 0x20-0x23 Endpoints0-3 FIFOs 186
Indexed Registers
E0CSR
0x11
Endpoint0 Control / Status 199
EINCSRL Endpoint IN Control / Status Low Byte 203
EINCSRH 0x12 Endpoint IN Control / Status High Byte 204
EOUTCSRL 0x14 Endpoint OUT Control / Status Low Byte 206
EOUTCSRH 0x15 Endpoint OUT Control / Status High Byte 207
E0CNT
0x16
Number of Received Bytes in Endpoint0 FIFO 200
EOUTCNTL Endpoint OUT Packet Count Low Byte 207
EOUTCNTH 0x17 Endpoint OUT Packet Count High Byte 208
C8051F380/1/2/3/4/5/6/7/C
183 Rev. 1.5
USB Register Address = 0x0E
21.4. USB Clock Configuration
USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is
selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock
must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options
are described in Section “19. Oscillators and Clock Selection” on page 146. The USB0 clock is selected via
SFR CLKSEL (see SFR Definition 19.1).
Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows
the internal oscillator to meet the requirements for USB clock tolerance. Clock Recovery should be used in
the following configurations:
When operating USB0 as a Low Speed function with Clock Recovery, software must write 1 to the CRLOW
bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode.
Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are pres-
ent on the USB network. This mode is not required (or recommended) in typical USB environments.
USB Register Definition 21.4. INDEX: USB0 Endpoint Index
Bit76543210
Name
EPSEL[3:0]
Type RRRR R/W
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3:0 EPSEL[3:0]
Endpoint Select Bits.
These bits select which endpoint is targeted when indexed USB0 registers are
accessed.
0000: Endpoint 0
0001: Endpoint 1
0010: Endpoint 2
0011: Endpoint 3
0100-1111: Reserved.
Communication Speed USB Clock
Full Speed Internal Oscillator
Low Speed Internal Oscillator / 8
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 184
USB Register Address = 0x0F
USB Register Definition 21.5. CLKREC: Clock Recovery Control
Bit76543210
Name
CRE CRSSEN CRLOW
Type R/W R/W R/W R/W
Reset 00001111
Bit Name Function
7 CRE Clock Recovery Enable Bit.
This bit enables/disables the USB clock recovery feature.
0: Clock recovery disabled.
1: Clock recovery enabled.
6 CRSSEN
Clock Recovery Single Step.
This bit forces the oscillator calibration into single-step mode during clock
recovery.
0: Normal calibration mode.
1: Single step mode.
5CRLOW
Low Speed Clock Recovery Mode.
This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB
device.
0: Full Speed Mode.
1: Low Speed Mode.
4:0 Reserved Must Write = 01111b.
C8051F380/1/2/3/4/5/6/7/C
185 Rev. 1.5
21.5. FIFO Management
1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between End-
points0-3 as shown in Figure 21.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or
both (Split Mode: half IN, half OUT).
Figure 21.3. USB FIFO Allocation
21.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is config-
ured for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256
bytes (0x0440 to 0x053F) are used by Endpoint3 OUT.
If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to
form a single IN
or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see SFR Definition 21.13).
Endpoint0
(64 bytes)
Configurable as
IN, OUT, or both (Split
Mode)
Free
(64 bytes)
0x0400
0x043F
0x0440
0x063F
0x0640
0x073F
0x0740
0x07BF
0x07C0
0x07FF
User XRAM
(1024 bytes)
0x0000
0x03FF
USB Clock Domain
System Clock Domain
Endpoint1
(128 bytes)
Endpoint2
(256 bytes)
Endpoint3
(512 bytes)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 186
21.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for End-
points1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN End-
point and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for the
entire endpoint FIFO. See Table 21.3 for a list of maximum packet sizes for each FIFO configuration.
21.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
USB Register Address = 0x20-0x23
Table 21.3. FIFO Configurations
Endpoint
Number
Split Mode
Enabled?
Maximum IN Packet Size
(Double Buffer Disabled /
Enabled)
Maximum OUT Packet Size
(Double Buffer Disabled /
Enabled)
0N/A 64
1
N 128 / 64
Y 64 / 32 64 / 32
2
N 256 / 128
Y 128 / 64 128 / 64
3
N 512 / 256
Y 256 / 128 256 / 128
USB Register Definition 21.6. FIFOn: USB0 Endpoint FIFO Access
Bit76543210
Name
FIFODATA[7:0]
Type R/W
Reset 0000000
0
Bit Name Function
7:0 FIFODATA[7:0] Endpoint FIFO Access Bits.
USB Addresses 0x20-0x23 provide access to the 4 pairs of endpoint FIFOs:
0x20: Endpoint 0
0x21: Endpoint 1
0x22: Endpoint 2
0x23: Endpoint 3
Writing to the FIFO address loads data into the IN FIFO for the corresponding
endpoint. Reading from the FIFO address unloads data from the OUT FIFO for
the corresponding endpoint.
C8051F380/1/2/3/4/5/6/7/C
187 Rev. 1.5
21.6. Function Addressing
The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-
bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new
address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of
the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The
UPDATE bit (FADDR.7) is set to 1 by hardware when software writes a new address to the FADDR regis-
ter. Hardware clears the UPDATE bit when the new address takes effect as described above.
USB Register Address = 0x00
21.7. Function Configuration and Control
The USB register POWER (USB Register Definition 21.8) is used to configure and control USB0 at the
device level (enable/disable, Reset/Suspend/Resume handling, etc.).
USB Reset: The USBRST bit (POWER.3) is set to 1 by hardware when Reset signaling is detected on the
bus. Upon this detection, the following occur:
1. The USB0 Address is reset (FADDR = 0x00).
2. Endpoint FIFOs are flushed.
3. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH).
4. USB register INDEX is reset to 0x00.
5. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared.
6. A USB Reset interrupt is generated if enabled.
Writing a 1 to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to
their default values following this asynchronous reset.
Suspend Mode: With Suspend Detection enabled (SUSEN = 1), USB0 will enter Suspend Mode when
Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = 1). The
USB Register Definition 21.7. FADDR: USB0 Function Address
Bit76543210
Name
UPDATE FADDR[6:0]
Type RR/W
Reset 00000000
Bit Name Function
7UPDATEFunction Address Update Bit.
Set to 1 when software writes the FADDR register. USB0 clears this bit to 0 when the
new address takes effect.
0: The last address written to FADDR is in effect.
1: The last address written to FADDR is not yet in effect.
6:0 FADDR[6:0]
Function Address Bits.
Holds the 7-bit function address for USB0. This address should be written by software
when the SET_ADDRESS standard device request is received on Endpoint0. The
new address takes effect when the device request completes.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 188
Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as
disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section
“19.3. Programmable Internal High-Frequency (H-F) Oscillator” on page 149 for more details on internal
oscillator configuration, including the Suspend mode feature of the internal oscillator.
USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or gener-
ated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscil-
lator will exit Suspend mode upon any of the above listed events.
Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume
interrupt will be generated upon detection if enabled (RESINTE = 1). Software may force a Remote
Wakeup by writing 1 to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should
write RESUME = 0 to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME =
1).
ISO Update: When software writes 1 to the ISOUP bit (POWER.7), the ISO Update function is enabled.
With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new
Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will
transmit a zero-length packet. When ISOUP = 1, ISO Update is enabled for all ISO endpoints.
USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the
USBINH bit (POWER.4). Once written to 0, the USBINH can only be set to 1 by one of the following: (1) a
Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing 1 to the USBRST bit
(POWER.3).
Software should perform all USB0 configuration before enabling USB0. The configuration sequence
should be performed as follows:
1. Select and enable the USB clock source.
2. Reset USB0 by writing USBRST= 1.
3. Configure and enable the USB Transceiver.
4. Perform any USB0 function configuration (interrupts, Suspend detect).
5. Enable USB0 by writing USBINH = 0.
C8051F380/1/2/3/4/5/6/7/C
189 Rev. 1.5
USB Register Address = 0x01
USB Register Definition 21.8. POWER: USB0 Power
Bit76543210
Name
ISOUD USBINH USBRST RESUME SUSMD SUSEN
Type R/W R/W R/W R/W R/W R/W R R/W
Reset 00000000
Bit Name Function
7ISOUDISO Update Bit.
This bit affects all IN Isochronous endpoints.
0: When software writes INPRDY = 1, USB0 will send the packet when the next IN token
is received.
1: When software writes INPRDY = 1, USB0 will wait for a SOF token before sending the
packet. If an IN token is received before a SOF token, USB0 will send a zero-length data
packet.
6:5 Unused Read = 00b. Write = don’t care.
4 USBINH
USB0 Inhibit Bit.
This bit is set to 1 following a power-on reset (POR) or an asynchronous USB0 reset.
Software should clear this bit after all USB0 transceiver initialization is complete. Soft-
ware cannot set this bit to 1.
0: USB0 enabled.
1: USB0 inhibited. All USB traffic is ignored.
3 USBRST
Reset Detect. Read:
0: Reset signaling is not present.
1: Reset signaling detected on
the bus.
Write:
Writing 1 to this bit forces an
asynchronous USB0 reset.
2 RESUME
Force Resume.
Writing a 1 to this bit while in Suspend mode (SUSMD = 1) forces USB0 to generate
Resume signaling on the bus (a remote wakeup event). Software should write RESUME
= 0 after 10 to 15 ms to end the Resume signaling. An interrupt is generated, and hard-
ware clears SUSMD, when software writes RESUME = 0.
1SUSMD
Suspend Mode.
Set to 1 by hardware when USB0 enters suspend mode. Cleared by hardware when soft-
ware writes RESUME = 0 (following a remote wakeup) or reads the CMINT register after
detection of Resume signaling on the bus.
0: USB0 not in suspend mode.
1: USB0 in suspend mode.
0 SUSEN
Suspend Detection Enable.
0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus.
1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend sig-
naling on the bus.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 190
USB Register Address = 0x0C
USB Register Address = 0x0D
21.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in USB Register
Definition 21.11 through USB Register Definition 21.13. The associated interrupt enable bits are located in
the USB registers shown in USB Register Definition 21.14 through USB Register Definition 21.16. A USB0
interrupt is generated when any of the USB interrupt flags is set to 1. The USB0 interrupt is enabled via the
EIE1 SFR (see Section “16. Interrupts” on page 122).
Important Note: Reading a USB interrupt flag register resets all flags in that register to 0.
USB Register Definition 21.9. FRAMEL: USB0 Frame Number Low
Bit76543210
Name
FRMEL[7:0]
Type R
Reset 00000000
Bit Name Function
7:0 FRMEL[7:0] Frame Number Low Bits.
This register contains bits 7-0 of the last received frame number.
USB Register Definition 21.10. FRAMEH: USB0 Frame Number High
Bit76543210
Name
FRMEH[2:0]
Type RRRRR R
Reset 00000000
Bit Name Function
7:3 Unused Read = 00000b. Write = don’t care.
2:0 FRMEH[2:0]
Frame Number High Bits.
This register contains bits 10-8 of the last received frame number.
C8051F380/1/2/3/4/5/6/7/C
191 Rev. 1.5
USB Register Address = 0x02
USB Register Definition 21.11. IN1INT: USB0 IN Endpoint Interrupt
Bit76543210
Name
IN3 IN2 IN1 EP0
Type RRRRRRRR
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3IN3
IN Endpoint 3 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 3 interrupt inactive.
1: IN Endpoint 3 interrupt active.
2IN2
IN Endpoint 2 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 2 interrupt inactive.
1: IN Endpoint 2 interrupt active.
1IN1
IN Endpoint 1 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 1 interrupt inactive.
1: IN Endpoint 1 interrupt active.
0 EP0
Endpoint 0 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: Endpoint 0 interrupt inactive.
1: Endpoint 0 interrupt active.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 192
USB Register Address = 0x04
USB Register Definition 21.12. OUT1INT: USB0 OUT Endpoint Interrupt
Bit76543210
Name
OUT3 OUT2 OUT1
Type RRRRRRRR
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3OUT3
OUT Endpoint 3 Interrupt-Pending Flag.
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 3 interrupt inactive.
1: OUT Endpoint 3 interrupt active.
2OUT2
OUT Endpoint 2 Interrupt-Pending Flag.
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 2 interrupt inactive.
1: OUT Endpoint 2 interrupt active.
1OUT1
OUT Endpoint 1 Interrupt-Pending Flag.
This bit is cleared when software reads the OUT1INT register.
0: OUT Endpoint 1 interrupt inactive.
1: OUT Endpoint 1 interrupt active.
0 Unused Read = 0b. Write = don’t care.
C8051F380/1/2/3/4/5/6/7/C
193 Rev. 1.5
USB Register Address = 0x06
USB Register Definition 21.13. CMINT: USB0 Common Interrupt
Bit76543210
Name
SOF RSTINT RSUINT SUSINT
Type RRRRRRRR
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3SOF
Start of Frame Interrupt Flag.
Set by hardware when a SOF token is received. This interrupt event is synthesized by
hardware: an interrupt will be generated when hardware expects to receive a SOF
event, even if the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
2RSTINT
Reset Interrupt-Pending Flag.
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
1RSUINT
Resume Interrupt-Pending Flag.
Set by hardware when Resume signaling is detected on the bus while USB0 is in sus-
pend mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
0SUSINT
Suspend Interrupt-Pending Flag.
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by
hardware when Suspend signaling is detected on the bus. This bit is cleared when
software reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 194
USB Register Address = 0x07
USB Register Definition 21.14. IN1IE: USB0 IN Endpoint Interrupt Enable
Bit76543210
Name
IN3E IN2E IN1E EP0E
Type RRRRR/WR/WR/WR/W
Reset 00001111
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3IN3E
IN Endpoint 3 Interrupt Enable.
0: IN Endpoint 3 interrupt disabled.
1: IN Endpoint 3 interrupt enabled.
2IN2E
IN Endpoint 2 Interrupt Enable.
0: IN Endpoint 2 interrupt disabled.
1: IN Endpoint 2 interrupt enabled.
1IN1E
IN Endpoint 1 Interrupt Enable.
0: IN Endpoint 1 interrupt disabled.
1: IN Endpoint 1 interrupt enabled.
0 EP0E
Endpoint 0 Interrupt Enable.
0: Endpoint 0 interrupt disabled.
1: Endpoint 0 interrupt enabled.
C8051F380/1/2/3/4/5/6/7/C
195 Rev. 1.5
USB Register Address = 0x09
USB Register Definition 21.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable
Bit76543210
Name
OUT3E OUT2E OUT1E
Type RRRRR/WR/WR/WR
Reset 00001110
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3OUT3E
OUT Endpoint 3 Interrupt Enable.
0: OUT Endpoint 3 interrupt disabled.
1: OUT Endpoint 3 interrupt enabled.
2OUT2E
OUT Endpoint 2 Interrupt Enable.
0: OUT Endpoint 2 interrupt disabled.
1: OUT Endpoint 2 interrupt enabled.
1OUT1E
OUT Endpoint 1 Interrupt Enable.
0: OUT Endpoint 1 interrupt disabled.
1: OUT Endpoint 1 interrupt enabled.
0 Unused Read = 0b. Write = don’t care.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 196
USB Register Address = 0x0B
USB Register Definition 21.16. CMIE: USB0 Common Interrupt Enable
Bit76543210
Name
SOFE RSTINTE RSUINTE SUSINTE
Type RRRRR/WR/WR/WR/W
Reset 00000110
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3SOFE
Start of Frame Interrupt Enable.
0: SOF interrupt disabled.
1: SOF interrupt enabled.
2RSTINTE
Reset Interrupt Enable.
0: Reset interrupt disabled.
1: Reset interrupt enabled.
1RSUINTE
Resume Interrupt Enable.
0: Resume interrupt disabled.
1: Resume interrupt enabled.
0SUSINTE
Suspend Interrupt Enable.
0: Suspend interrupt disabled.
1: Suspend interrupt enabled.
C8051F380/1/2/3/4/5/6/7/C
197 Rev. 1.5
21.9. The Serial Interface Engine
The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor
when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the
processor when a complete data packet has been received; appropriate handshaking signals are automat-
ically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete
data packet has been transmitted and the appropriate handshake signal has been received.
The SIE will not interrupt the processor when corrupted/erroneous packets are received.
21.10. Endpoint0
Endpoint0 is managed through the USB register E0CSR (USB Register Definition 21.18). The INDEX reg-
ister must be loaded with 0x00 to access the E0CSR register.
An Endpoint0 interrupt is generated when:
1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY
bit (E0CSR.0) is set to 1 by hardware.
2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the
host; INPRDY is reset to 0 by hardware.
3. An IN transaction is completed (this interrupt generated during the status stage of the transaction).
4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation.
5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the
DATAEND bit (E0CSR.3).
The E0CNT register (USB Register Definition 21.11) holds the number of received data bytes in the End-
point0 FIFO.
Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may
force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit
will be set to 1 and an interrupt generated. The following conditions will cause hardware to generate a
STALL condition:
1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to 1.
2. The host sends an IN token during an IN data phase after the DATAEND bit has been set to 1.
3. The host sends a packet that exceeds the maximum packet size for Endpoint0.
4. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction.
Firmware sets the SDSTL bit (E0CSR.5) to 1.
21.10.1. Endpoint0 SETUP Transactions
All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, con-
taining an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything
other than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the
data from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from
the Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indi-
cate that it has serviced the OUT packet.
21.10.2. Endpoint0 IN Transactions
When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN
requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the
Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is
transmitted successfully. Note that no interrupt will be generated if an IN request is received before firm-
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 198
ware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet
size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet
should be of the maximum packet size excluding the last (residual) packet. If the requested data is an inte-
ger multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet
signaling the end of the transfer. Firmware should set the DATAEND bit to 1 after loading into the End-
point0 FIFO the last data packet for a transfer.
Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit
Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is
set to 1 if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode.
Endpoint0 will remain in Transmit Mode until any of the following occur:
1. USB0 receives an Endpoint0 SETUP or OUT token.
2. Firmware sends a packet less than the maximum Endpoint0 packet size.
3. Firmware sends a zero-length packet.
Firmware should set the DATAEND bit (E0CSR.3) to 1 when performing (2) and (3) above.
The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY
= 0).
21.10.3. Endpoint0 OUT Transactions
When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT
requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will
set the OPRDY bit (E0CSR.0) to 1 and generate an Endpoint0 interrupt. Following this interrupt, firmware
should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to 1.
If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data
will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size
for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the
transfer.
Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive
Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4)
is set to 1 if a SETUP or IN token is received while Endpoint0 is in Receive Mode.
Endpoint0 will remain in Receive mode until:
1. The SIE receives a SETUP or IN token.
2. The host sends a packet less than the maximum Endpoint0 packet size.
3. The host sends a zero-length packet.
Firmware should set the DATAEND bit (E0CSR.3) to 1 when the expected amount of data has been
received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit
has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to 1 after the
STALL is transmitted.
C8051F380/1/2/3/4/5/6/7/C
199 Rev. 1.5
USB Register Address = 0x11
USB Register Definition 21.17. E0CSR: USB0 Endpoint0 Control
Bit76543210
Name
SSUEND SOPRDY SDSTL SUEND DATAEND STSTL INPRDY OPRDY
Type R/W R/W R/W R R/W R/W R/W R
Reset 00000000
Bit Name Description Write Read
7 SSUEND Serviced Setup End
Bit.
Software should set this bit to 1
after servicing a Setup End (bit
SUEND) event. Hardware clears
the SUEND bit when software
writes 1 to SSUEND.
This bit always reads 0.
6SOPRDY
Serviced OPRDY Bit. Software should write 1 to this bit
after servicing a received End-
point0 packet. The OPRDY bit will
be cleared by a write of 1 to
SOPRDY.
This bit always reads 0.
5SDSTL
Send Stall Bit.
Software can write 1 to this bit to terminate the current transfer (due to an error condi-
tion, unexpected transfer request, etc.). Hardware will clear this bit to 0 when the STALL
handshake is transmitted.
4 SUEND
Setup End Bit.
Hardware sets this read-only bit to 1 when a control transaction ends before software
has written 1 to the DATAEND bit. Hardware clears this bit when software writes 1 to
SSUEND.
3 DATAEND
Data End Bit.
Software should write 1 to this bit: 1) When writing 1 to INPRDY for the last outgoing
data packet. 2) When writing 1 to INPRDY for a zero-length data packet. 3) When writ-
ing 1 to SOPRDY after servicing the last incoming data packet.
This bit is automatically cleared by hardware.
2 STSTL
Sent Stall Bit.
Hardware sets this bit to 1 after transmitting a STALL handshake signal. This flag must
be cleared by software.
1 INPRDY
IN Packet Ready Bit.
Software should write 1 to this bit after loading a data packet into the Endpoint0 FIFO
for transmit. Hardware clears this bit and generates an interrupt under either of the fol-
lowing conditions: 1) The packet is transmitted. 2) The packet is overwritten by an
incoming SETUP packet. 3) The packet is overwritten by an incoming OUT packet.
0 OPRDY
OUT Packet Ready Bit.
Hardware sets this read-only bit and generates an interrupt when a data packet has
been received. This bit is cleared only when software writes 1 to the SOPRDY bit.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 200
USB Register Address = 0x16
21.11. Configuring Endpoints1-3
Endpoints1-3 are configured and controlled through their own sets of the following control/status registers:
IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of
endpoint control/status registers is mapped into the USB register address space at a time, defined by the
contents of the INDEX register (USB Register Definition 21.4).
Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 21.5.1.
The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.
When SPLIT = 1, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.
When SPLIT = 0, the corresponding endpoint functions as either IN or OUT; the endpoint direction is
selected by the DIRSEL bit in register EINCSRH.
Endpoints1-3 can be disabled individually by the corresponding bits in the ENABLE register. When an
Endpoint is disabled, it will not respond to bus traffic or stall the bus. All Endpoints are enabled by default.
USB Register Definition 21.18. E0CNT: USB0 Endpoint0 Data Count
Bit76543210
Name
E0CNT[6:0]
Type RR
Reset 00000000
Bit Name Function
7 Unused Read = 0b. Write = don’t care.
6:0 E0CNT[6:0]
Endpoint 0 Data Count.
This 7-bit number indicates the number of received data bytes in the Endpoint 0
FIFO. This number is only valid while bit OPRDY is a 1.
C8051F380/1/2/3/4/5/6/7/C
201 Rev. 1.5
USB Register Address = 0x1E
21.12. Controlling Endpoints1-3 IN
Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used
for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the ISO bit
in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 IN interrupt is generated by any of the following conditions:
1. An IN packet is successfully transferred to the host.
2. Software writes 1 to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
3. Hardware generates a STALL condition.
21.12.1. Endpoints1-3 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt Mode. Once an end-
point has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_IN-
TERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY
bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and
generate an interrupt.
Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be
transmitted upon reception of the next IN token.
USB Register Definition 21.19. EENABLE: USB0 Endpoint Enable
Bit76543210
Name
EEN3 EEN2 EEN1
Type RRRRR/WR/WR/WR/W
Reset 11111111
Bit Name Function
7:4 Unused Read = 1111b. Write = don’t care.
3 EEN3
Endpoint 3 Enable.
This bit enables/disables Endpoint 3.
0: Endpoint 3 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 3 is enabled (normal).
2 EEN2
Endpoint 2 Enable.
This bit enables/disables Endpoint 2.
0: Endpoint 2 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 2 is enabled (normal).
1 EEN1
Endpoint 1 Enable.
This bit enables/disables Endpoint 1.
0: Endpoint 1 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 1 is enabled (normal).
0 Reserved Must Write 1b.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 202
A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EINCSRL.4). While
SDSTL = 1, hardware will respond to all IN requests with a STALL condition. Each time hardware gener-
ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to 1. The
STSTL bit must be reset to 0 by firmware.
Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO. Note that
if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the
IN FIFO at a time. In this case, hardware will reset INPRDY to 0 immediately after firmware loads the first
packet into the FIFO and sets INPRDY to 1. An interrupt will not be generated in this case; an interrupt will
only be generated when a data packet is transmitted.
When firmware writes 1 to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled
continuously, regardless of the handshake received from the host. This feature is typically used by Inter-
rupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = 0,
the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet.
21.12.2. Endpoints1-3 IN Isochronous Mode
When the ISO bit (EINCSRH.6) is set to 1, the target endpoint operates in Isochronous (ISO) mode. Once
an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per
frame; the location of data within each frame may vary. Because of this, it is recommended that double
buffering be enabled for ISO IN endpoints.
Hardware will automatically reset INPRDY (EINCSRL.0) to 0 when a packet slot is open in the endpoint
FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two
packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to 0 immediately after firm-
ware loads the first packet into the FIFO and sets INPRDY to 1. An interrupt will not be generated in this
case; an interrupt will only be generated when a data packet is transmitted.
If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host,
USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to 1.
The ISO Update feature (see Section 21.7) can be useful in starting a double buffered ISO IN endpoint. If
the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the
first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before
firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature
ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame;
the packet will only be sent after a SOF signal has been received.
C8051F380/1/2/3/4/5/6/7/C
203 Rev. 1.5
USB Register Address = 0x11
USB Register Definition 21.20. EINCSRL: USB0 IN Endpoint Control Low
Bit76543210
Name
CLRDT STSTL SDSTL FLUSH UNDRUN FIFONE INPRDY
Type R W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Description Write Read
7 Unused Read = 0b. Write = don’t care.
6 CLRDT
Clear Data Toggle Bit. Software should write 1 to
this bit to reset the IN End-
point data toggle to 0.
This bit always reads 0.
5STSTL
Sent Stall Bit.
Hardware sets this bit to 1 when a STALL handshake signal is transmitted. The FIFO is
flushed, and the INPRDY bit cleared. This flag must be cleared by software.
4SDSTL
Send Stall.
Software should write 1 to this bit to generate a STALL handshake in response to an IN
token. Software should write 0 to this bit to terminate the STALL signal. This bit has no
effect in ISO mode.
3FLUSH
FIFO Flush Bit.
Writing a 1 to this bit flushes the next packet to be transmitted from the IN Endpoint
FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains mul-
tiple packets, software must write 1 to FLUSH for each packet. Hardware resets the
FLUSH bit to 0 when the FIFO flush is complete.
2 UNDRUN
Data Underrun Bit.
The function of this bit depends on the IN Endpoint mode:
ISO: Set when a zero-length packet is sent after an IN token is received while bit
INPRDY = 0.
Interrupt/Bulk: Set when a NAK is returned in response to an IN token.
This bit must be cleared by software.
1FIFONE
FIFO Not Empty.
0: The IN Endpoint FIFO is empty.
1. The IN Endpoint FIFO contains one or more packets.
0 INPRDY
In Packet Ready.
Software should write 1 to this bit after loading a data packet into the IN Endpoint FIFO.
Hardware clears INPRDY due to any of the following: 1) A data packet is transmitted. 2)
Double buffering is enabled (DBIEN = 1) and there is an open FIFO packet slot. 3) If the
endpoint is in Isochronous Mode (ISO = 1) and ISOUD = 1, INPRDY will read 0 until the
next SOF is received.
Note: An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a
packet being transmitted.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 204
USB Register Address = 0x12
USB Register Definition 21.21. EINCSRH: USB0 IN Endpoint Control High
Bit76543210
Name
DBIEN ISO DIRSEL FCDT SPLIT
Type R/W R/W R/W R R/W R/W R R
Reset 00000000
Bit Name Function
7DBIENIN Endpoint Double-buffer Enable.
0: Double-buffering disabled for the selected IN endpoint.
1: Double-buffering enabled for the selected IN endpoint.
6ISO
Isochronous Transfer Enable.
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
5 DIRSEL
Endpoint Direction Select.
This bit is valid only when the selected FIFO is not split (SPLIT = 0).
0: Endpoint direction selected as OUT.
1: Endpoint direction selected as IN.
4 Unused Read = 0b. Write = don’t care.
3FCDT
Force Data Toggle Bit.
0: Endpoint data toggle switches only when an ACK is received following a data packet
transmission.
1: Endpoint data toggle forced to switch after every data packet is transmitted, regard-
less of ACK reception.
2 SPLIT
FIFO Split Enable.
When SPLIT = 1, the selected endpoint FIFO is split. The upper half of the selected
FIFO is used by the IN endpoint; the lower half of the selected FIFO is used by the OUT
endpoint.
1:0 Unused Read = 00b. Write = don’t care.
C8051F380/1/2/3/4/5/6/7/C
205 Rev. 1.5
21.13. Controlling Endpoints1-3 OUT
Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can
be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the
ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 OUT interrupt may be generated by the following:
1. Hardware sets the OPRDY bit (EINCSRL.0) to 1.
2. Hardware generates a STALL condition.
21.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode
When the ISO bit (EOUTCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt mode. Once an
endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0
SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to 1 and generate an
interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data
packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL reg-
isters. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset
the OPRDY bit to 0.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing 1 to the SDSTL bit (EOUTCSRL.5). While
SDSTL = 1, hardware will respond to all OUT requests with a STALL condition. Each time hardware gener-
ates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to 1. The
STSTL bit must be reset to 0 by firmware.
Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buff-
ering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a
time. In this case, hardware will set OPRDY to 1 immediately after firmware unloads the first packet and
resets OPRDY to 0. A second interrupt will be generated in this case.
21.13.2. Endpoints1-3 OUT Isochronous Mode
When the ISO bit (EOUTCSRH.6) is set to 1, the target endpoint operates in Isochronous (ISO) mode.
Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB
frame; the location of the data packet within each frame may vary, however. Because of this, it is recom-
mended that double buffering be enabled for ISO OUT endpoints.
Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO,
set the OPRDY bit (EOUTCSRL.0) to 1, and generate an interrupt (if enabled). Firmware would typically
use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to 0.
If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and
the OVRUN bit (EOUTCSRL.2) set to 1. If USB0 receives an ISO data packet with a CRC error, the data
packet will be loaded into the endpoint FIFO, OPRDY will be set to 1, an interrupt (if enabled) will be gen-
erated, and the DATAERR bit (EOUTCSRL.3) will be set to 1. Software should check the DATAERR bit
each time a data packet is unloaded from an ISO OUT endpoint FIFO.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 206
USB Register Address = 0x14
USB Register Definition 21.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte
Bit76543210
Name
CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY
Type W R/W R/W R/W R R/W R R/W
Reset 00000000
Bit Name Description Write Read
7 CLRDT Clear Data Toggle Bit. Software should write 1 to
this bit to reset the OUT end-
point data toggle to 0.
This bit always reads 0.
6STSTL
Sent Stall Bit.
Hardware sets this bit to 1 when a STALL handshake signal is transmitted. This flag
must be cleared by software.
5SDSTL
Send Stall Bit.
Software should write 1 to this bit to generate a STALL handshake. Software should
write 0 to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
4FLUSH
FIFO Flush Bit.
Writing a 1 to this bit flushes the next packet to be read from the OUT endpoint FIFO.
The FIFO pointer is reset and the OPRDY bit is cleared. Multiple packets must be
flushed individually. Hardware resets the FLUSH bit to 0 when the flush is complete.
Note: If data for the current packet has already been read from the FIFO, the FLUSH bit should
not be used to flush the packet. Instead, the FIFO should be read manually.
3DATERRData Error Bit.
In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing
error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode.
2 OVRUN
Data Overrun Bit.
This bit is set by hardware when an incoming data packet cannot be loaded into the
OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software.
0: No data overrun.
1: A data packet was lost because of a full FIFO since this flag was last cleared.
1FIFOFUL
OUT FIFO Full.
This bit indicates the contents of the OUT FIFO. If double buffering is enabled (DBIEN =
1), the FIFO is full when the FIFO contains two packets. If DBIEN = 0, the FIFO is full
when the FIFO contains one packet.
0: OUT endpoint FIFO is not full.
1: OUT endpoint FIFO is full.
0OPRDY
OUT Packet Ready.
Hardware sets this bit to 1 and generates an interrupt when a data packet is available.
Software should clear this bit after each data packet is unloaded from the OUT endpoint
FIFO.
C8051F380/1/2/3/4/5/6/7/C
207 Rev. 1.5
USB Register Address = 0x15
USB Register Address = 0x16
USB Register Definition 21.23. EOUTCSRH: USB0 OUT Endpoint Control High
Byte
Bit76543210
Name
DBOEN ISO
Type R/WR/WRRRRRR
Reset 00000000
Bit Name Function
7DBOENDouble-buffer Enable.
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
6ISO
Isochronous Transfer Enable.
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
5:0 Unused Read = 000000b. Write = don’t care.
USB Register Definition 21.24. EOUTCNTL: USB0 OUT Endpoint Count Low
Bit76543210
Name
EOCL[7:0]
Type R
Reset 00000000
Bit Name Function
7:0 EOCL[7:0] OUT Endpoint Count Low Byte.
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received
packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 208
USB Register Address = 0x17
USB Register Definition 21.25. EOUTCNTH: USB0 OUT Endpoint Count High
Bit76543210
Name
EOCH[1:0]
Type RRRRRRRR
Reset 00000000
Bit Name Function
7:2 Unused Read = 000000b. Write = don’t care.
1:0 EOCH[1:0]
OUT Endpoint Count High Byte.
EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received
packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1.
C8051F380/1/2/3/4/5/6/7/C
209 Rev. 1.5
22. SMBus0 and SMBus1 (I
2
C Compatible)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I
2
C serial bus. The
C8051F380/1/2/3/4/5/6/7/C devices contain two SMBus interfaces, SMBus0 and SMBus1.
Reads and writes to the SMBus by the system controller are byte oriented with the SMBus interface auton-
omously controlling the serial transfer of the data. Data can be transferred at up to 1/20th of the system
clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the
system clock used). A method of extending the clock-low duration is available to accommodate devices
with different speed capabilities on the same bus.
The SMBus may operate as a master and/or slave, and may function on a bus with multiple masters. The
SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration
logic, and START/STOP control and generation. The SMBus peripherals can be fully driven by software
(i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address recogni-
tion and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the
SMBus0 peripheral and the associated SFRs is shown in Figure 22.1. SMBus1 is identical,with the excep-
tion of the available timer options for the clock source, and the timer used to implement the SCL low time-
out feature. Refer to the specific SFR definitions for more details.
Figure 22.1. SMBus Block Diagram
Data Path
Control
SMBUS CONTROL LOGIC
C
R
O
S
S
B
A
R
SCL
FILTER
N
SDA
Control
SCL
Control
Interrupt
Request
Port I/O
SMB0CN
S
T
A
A
C
K
R
Q
A
R
B
L
O
S
T
A
C
K
S
I
T
X
M
O
D
E
M
A
S
T
E
R
S
T
O
01
00
10
11
T0 Overflow
T1 Overflow (SMBus0) or T5 Overflow (SMBus1)
TMR2H Overflow
TMR2L Overflow
SMB0CF
E
N
S
M
B
I
N
H
B
U
S
Y
E
X
T
H
O
L
D
S
M
B
T
O
E
S
M
B
F
T
E
S
M
B
C
S
1
S
M
B
C
S
0
01234567
SMB0DAT
SDA
FILTER
N
SMB0ADR
S
L
V
4
S
L
V
2
S
L
V
1
S
L
V
0
G
C
S
L
V
5
S
L
V
6
S
L
V
3
SMB0ADM
S
L
V
M
4
S
L
V
M
2
S
L
V
M
1
S
L
V
M
0
E
H
A
C
K
S
L
V
M
5
S
L
V
M
6
S
L
V
M
3
Arbitration
SCL Synchronization
Hardware ACK Generation
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
IRQ Generation
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 210
22.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
The I
2
C-Bus and How to Use It (including specifications), Philips Semiconductor.
The I
2
C-Bus Specification—Version 2.0, Philips Semiconductor.
System Management Bus Specification—Version 1.1, SBS Implementers Forum.
22.2. SMBus Configuration
Figure 22.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Figure 22.2. Typical SMBus Configuration
22.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. It is not necessary to specify one device
as the Master in a system; any device who transmits a START and a slave address becomes the master
for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 22.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
VDD = 5V
Master
Device
Slave
Device 1
Slave
Device 2
VDD = 3V VDD = 5V VDD = 3V
SDA
SCL
C8051F380/1/2/3/4/5/6/7/C
211 Rev. 1.5
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 22.3 illustrates a typical
SMBus transaction.
Figure 22.3. SMBus Transaction
22.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
22.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “22.3.5. SCL High (SMBus Free) Timeout” on
page 212). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
22.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
22.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
For the SMBus0 interface, Timer 3 is used to implement SCL low timeouts. Timer 4 is used on the SMBus1
interface for SCL low timeouts. The SCL low timeout feature is enabled by setting the SMBnTOE bit in
SMBnCF. The associated timer is forced to reload when SCL is high, and allowed to count when SCL is
SLA6
SDA
SLA5-0 R/W D7 D6-0
SCL
Slave Address + R/W Data ByteSTART ACK NACK STOP
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 212
low. With the associated timer enabled and configured to overflow after 25 ms (and SMBnTOE set), the
timer interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an
SCL low timeout.
22.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBnFTE bit in SMBnCF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
22.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,
these interrupts are always generated after the ACK cycle. See Section 22.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMBnCN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMBnCN register is described in Section 22.4.3;
Table 22.5 provides a quick SMBnCN decoding reference.
22.4.1. SMBus Configuration Register
The SMBus Configuration register (SMBnCF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
C8051F380/1/2/3/4/5/6/7/C
213 Rev. 1.5
The SMBnCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 22.1.The selected
clock source may be shared by other peripherals so long as the timer is left running at all times. For exam-
ple, Timer 1 overflows may generate the SMBus0 and SMBus1 clock rates simultaneously. Timer configu-
ration is covered in Section “26. Timers” on page 263.
Equation 22.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 22.2.
Equation 22.2. Typical SMBus Bit Rate
Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that T
HIGH
is typically
twice as large as T
LOW
. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 22.1.
Figure 22.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 22.2 shows the min-
Table 22.1. SMBus Clock Source Selection
SMBnCS1 SMBnCS0 SMBus0 Clock Source SMBus1 Clock Source
0 0 Timer 0 Overflow Timer 0 Overflow
0 1 Timer 1 Overflow Timer 5 Overflow
1 0 Timer 2 High Byte Overflow Timer 2 High Byte Overflow
1 1 Timer 2 Low Byte Overflow Timer 2 Low Byte Overflow
T
HighMin
T
LowMin
1
f
ClockSourceOverflow
------------------------------------------------------------------==
BitRate
f
ClockSourceOverflow
3
------------------------------------------------------------------=
SCL
Timer Source
Overflows
SCL High TimeoutT
Low
T
High
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 214
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBnTOE bit set, Timer 3 (SMBus0) and Timer 5 (SMBus1) should be configured to overflow
after 25 ms in order to detect SCL low timeouts (see Section “22.3.4. SCL Low Timeout” on page 211). The
SMBus interface will force the associated timer to reload while SCL is high, and allow the timer to count
when SCL is low. The timer interrupt service routine should be used to reset SMBus communication by dis-
abling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBnFTE bit. When this bit is set, the bus
will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 22.4).
22.4.2. SMBus Timing Control Register
The SMBus Timing Control Register (SMBTC)is used to restrict the detection of a START condition under
certain circumstances. In some systems where there is significant mis-match between the impedance or
the capacitance on the SDA and SCL lines, it may be possible for SCL to fall after SDA during an address
or data transfer. Such an event can cause a false START detection on the bus. These kind of events are
not expected in a standard SMBus or I2C-compliant system.
In most systems this parameter should
not be adjusted, and it is recommended that it be left at its default value.
By default, if the SCL falling edge is detected after the falling edge of SDA (i.e. one SYSCLK cycle or
more), the device will detect this as a START condition. The SMBTC register is used to increase the
amount of hold time that is required between SDA and SCL falling before a START is recognized. An addi-
tional 2, 4, or 8 SYSCLKs can be added to prevent false START detection in systems where the bus con-
ditions warrant this.
Table 22.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time
0
T
low
– 4 system clocks
or
1 system clock + s/w delay
*
3 system clocks
1 11 system clocks 12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
C8051F380/1/2/3/4/5/6/7/C
215 Rev. 1.5
SFR Address = 0xC1; SFR Page = 0
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration
Bit765 4 3210
Name
ENSMB0 INH0 BUSY0 EXTHOLD0 SMB0TOE SMB0FTE SMB0CS[1:0]
Type R/W R/W R R/W R/W R/W R/W
Reset 000 0 0000
Bit Name Function
7ENSMB0SMBus0 Enable.
This bit enables the SMBus0 interface when set to 1. When enabled, the interface
constantly monitors the SDA0 and SCL0 pins.
6 INH0
SMBus0 Slave Inhibit.
When this bit is set to logic 1, the SMBus0 does not generate an interrupt when
slave events occur. This effectively removes the SMBus0 slave from the bus. Mas-
ter Mode interrupts are not affected.
5 BUSY0
SMBus0 Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4 EXTHOLD0
SMBus0 Setup and Hold Time Extension Enable.
This bit controls the SDA0 setup and hold times according to Table 22.2.
0: SDA0 Extended Setup and Hold Times disabled.
1: SDA0 Extended Setup and Hold Times enabled.
3SMB0TOE
SMBus0 SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus0 forces
Timer 3 to reload while SCL0 is high and allows Timer 3 to count when SCL0 goes
low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in
reload while SCL0 is high. Timer 3 should be programmed to generate interrupts at
25 ms, and the Timer 3 interrupt service routine should reset SMBus0 communica-
tion.
2SMB0FTE
SMBus0 Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL0 and SDA0
remain high for more than 10 SMBus clock source periods.
1:0 SMB0CS[1:0]
SMBus0 Clock Source Selection.
These two bits select the SMBus0 clock source, which is used to generate the
SMBus0 bit rate. The selected device should be configured according to
Equation 22.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 216
SFR Address = 0xC1; SFR Page = F
SFR Definition 22.2. SMB1CF: SMBus Clock/Configuration
Bit765 4 3210
Name
ENSMB1 INH1 BUSY1 EXTHOLD1 SMB1TOE SMB1FTE SMB1CS[1:0]
Type R/W R/W R R/W R/W R/W R/W
Reset 000 0 0000
Bit Name Function
7ENSMB1SMBus1 Enable.
This bit enables the SMBus1 interface when set to 1. When enabled, the interface
constantly monitors the SDA1 and SCL1 pins.
6 INH1
SMBus1 Slave Inhibit.
When this bit is set to logic 1, the SMBus1 does not generate an interrupt when
slave events occur. This effectively removes the SMBus1 slave from the bus. Mas-
ter Mode interrupts are not affected.
5 BUSY1
SMBus1 Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4 EXTHOLD1
SMBus1 Setup and Hold Time Extension Enable.
This bit controls the SDA1 setup and hold times according to Table 22.2.
0: SDA1 Extended Setup and Hold Times disabled.
1: SDA1 Extended Setup and Hold Times enabled.
3SMB1TOE
SMBus1 SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus1 forces
Timer 4 to reload while SCL1 is high and allows Timer 4 to count when SCL1 goes
low. If Timer 4 is configured to Split Mode, only the High Byte of the timer is held in
reload while SCL1 is high. Timer 4 should be programmed to generate interrupts at
25 ms, and the Timer 4 interrupt service routine should reset SMBus1 communica-
tion.
2SMB1FTE
SMBus1 Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL1 and SDA1
remain high for more than 10 SMBus clock source periods.
1:0 SMB1CS[1:0]
SMBus1 Clock Source Selection.
These two bits select the SMBus1 clock source, which is used to generate the
SMBus1 bit rate. The selected device should be configured according to
Equation 22.1.
00: Timer 0 Overflow
01: Timer 5 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
C8051F380/1/2/3/4/5/6/7/C
217 Rev. 1.5
SFR Address = 0xB9; SFR Page = F
SFR Definition 22.3. SMBTC: SMBus Timing Control
Bit76543210
Name
SMB1SDD[1:0] SMB0SDD[1:0]
Type RRRR R/W R/W
Reset 00000000
Bit Name Function
7:4 Unused
Read = 0000b; Write = don’t care.
3:2 SMB1SDD[1:0]
SMBus1 Start Detection Window
These bits increase the hold time requirement between SDA falling and SCL fall-
ing for START detection.
00: No additional hold time requirement (0-1 SYSCLK).
01: Increase hold time window to 2-3 SYSCLKs.
10: Increase hold time window to 4-5 SYSCLKs.
11: Increase hold time window to 8-9 SYSCLKs.
1:0 SMB0SDD[1:0]
SMBus0 Start Detection Window
These bits increase the hold time requirement between SDA falling and SCL fall-
ing for START detection.
00: No additional hold time window (0-1 SYSCLK).
01: Increase hold time window to 2-3 SYSCLKs.
10: Increase hold time window to 4-5 SYSCLKs.
11: Increase hold time window to 8-9 SYSCLKs.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 218
22.4.3. SMBnCN Control Register
SMBnCN is used to control the interface and to provide status information (see SFR Definition 22.4). The
higher four bits of SMBnCN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 22.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
22.4.3.1. Software ACK Generation
When the EHACK bit in register SMBnADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
22.4.3.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More detail about automatic slave address recognition can be found in Section 22.4.4.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 22.3 lists all sources for hardware changes to the SMBnCN bits. Refer to Table 22.5 for SMBus sta-
tus decoding using the SMBnCN register.
C8051F380/1/2/3/4/5/6/7/C
219 Rev. 1.5
SFR Address = 0xC0; SFR Page = 0; Bit-Addressable
SFR Definition 22.4. SMB0CN: SMBus Control
Bit 7 6 5 4 3 2 1 0
Name
MASTER0 TXMODE0 STA0 STO0 ACKRQ0 ARBLOST0 ACK0 SI0
Type R R R/W R/W R R R/W R/W
Reset 00000 000
Bit Name Description Read Write
7MASTER0SMBus0 Master/Slave
Indicator.
This read-only bit
indicates when the SMBus0 is
operating as a master.
0: SMBus0 operating in
slave mode.
1: SMBus0 operating in
master mode.
N/A
6 TXMODE0
SMBus0 Transmit Mode
Indicator.
This read-only bit
indicates when the SMBus0 is
operating as a transmitter.
0: SMBus0 in Receiver
Mode.
1: SMBus0 in Transmitter
Mode.
N/A
5STA0
SMBus0 Start Flag. 0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4STO0
SMBus0 Stop Flag. 0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or
pending (if in Master
Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3 ACKRQ0
SMBus0 Acknowledge
Request.
0: No ACK requested
1: ACK requested
N/A
2ARBLOST0
SMBus0 Arbitration Lost
Indicator.
0: No arbitration error.
1: Arbitration Lost
N/A
1ACK0
SMBus0 Acknowledge. 0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0SI0
SMBus0 Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI0 must be
cleared by software. While SI0
is set, SCL0 is held low and
the SMBus0 is stalled.
0: No interrupt pending
1: Interrupt Pending
0: Clear interrupt, and ini-
tiate next state machine
event.
1: Force interrupt.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 220
SFR Address = 0xC0; SFR Page = F; Bit-Addressable
SFR Definition 22.5. SMB1CN: SMBus Control
Bit 7 6 5 4 3 2 1 0
Name
MASTER1 TXMODE1 STA1 STO1 ACKRQ1 ARBLOST1 ACK1 SI1
Type R R R/W R/W R R R/W R/W
Reset 00000 000
Bit Name Description Read Write
7MASTER1SMBus1 Master/Slave
Indicator.
This read-only bit
indicates when the SMBus1 is
operating as a master.
0: SMBus1 operating in
slave mode.
1: SMBus1 operating in
master mode.
N/A
6 TXMODE1
SMBus1 Transmit Mode
Indicator.
This read-only bit
indicates when the SMBus1 is
operating as a transmitter.
0: SMBus1 in Receiver
Mode.
1: SMBus1 in Transmitter
Mode.
N/A
5STA1
SMBus1 Start Flag. 0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4STO1
SMBus1 Stop Flag. 0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or
pending (if in Master
Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3 ACKRQ1
SMBus1 Acknowledge
Request.
0: No ACK requested
1: ACK requested
N/A
2ARBLOST1
SMBus1 Arbitration Lost
Indicator.
0: No arbitration error.
1: Arbitration Lost
N/A
1ACK1
SMBus1 Acknowledge. 0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0SI1
SMBus1 Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI1 must be
cleared by software. While SI1
is set, SCL1 is held low and
the SMBus1 is stalled.
0: No interrupt pending
1: Interrupt Pending
0: Clear interrupt, and ini-
tiate next state machine
event.
1: Force interrupt.
C8051F380/1/2/3/4/5/6/7/C
221 Rev. 1.5
22.4.4. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 22.4.3.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register and the SMBus Slave Address Mask register. A single address or range of addresses
(including the General Call Address 0x00) can be specified using these two registers. The most-significant
seven bits of the two registers are used to define which addresses will be ACKed. A 1 in bit positions of the
slave address mask SLVM[6:0] enable a comparison between the received slave address and the hard-
ware’s slave address SLV[6:0] for those bits. A 0 in a bit of the slave address mask means that bit will be
treated as a “don’t care” for comparison purposes. In this case, either a 1 or a 0 value are acceptable on
Table 22.3. Sources for Hardware Changes to SMBnCN
Bit Set by Hardware When: Cleared by Hardware When:
MASTERn
A START is generated. A STOP is generated.
Arbitration is lost.
TXMODEn
START is generated.
SMBnDAT is written before the start of an
SMBus frame.
A START is detected.
Arbitration is lost.
SMBnDAT is not written before the
start of an SMBus frame.
STAn
A START followed by an address byte is
received.
Must be cleared by software.
STOn
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A pending STOP is generated.
ACKRQn
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
After each ACK cycle.
ARBLOSTn
A repeated START is detected as a
MASTER when STAn is low (unwanted
repeated START).
SCLn is sensed low while attempting to
generate a STOP or repeated START
condition.
SDAn is sensed low while transmitting a 1
(excluding ACK bits).
Each time SIn is cleared.
ACKn
The incoming ACK value is low
(ACKNOWLEDGE).
The incoming ACK value is high
(NOT ACKNOWLEDGE).
SIn
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Must be cleared by software.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 222
the incoming slave address. Additionally, if the GCn bit in register SMBnADR is set to 1, hardware will rec-
ognize the General Call Address (0x00). Table 22.4 shows some example parameter settings and the
slave addresses that will be recognized by hardware under those conditions.
SFR Address = 0xCF; SFR Page = 0
Table 22.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLVn[6:0]
Slave Address Mask
SLVMn[6:0]
GCn bit Slave Addresses Recognized by
Hardware
0x34 0x7F 0 0x34
0x34 0x7F 1 0x34, 0x00 (General Call)
0x34 0x7E 0 0x34, 0x35
0x34 0x7E 1 0x34, 0x35, 0x00 (General Call)
0x70 0x73 0 0x70, 0x74, 0x78, 0x7C
SFR Definition 22.6. SMB0ADR: SMBus0 Slave Address
Bit76543210
Name
SLV0[6:0] GC0
Type R/W R/W
Reset 00000000
Bit Name Function
7:1 SLV0[6:0] SMBus Hardware Slave Address.
Defines the SMBus0 Slave Address(es) for automatic hardware acknowledge-
ment. Only address bits which have a 1 in the corresponding bit position in
SLVM0[6:0] are checked against the incoming address. This allows multiple
addresses to be recognized.
0GC0
General Call Address Enable.
When hardware address recognition is enabled (EHACK0 = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
C8051F380/1/2/3/4/5/6/7/C
223 Rev. 1.5
SFR Address = 0xCE; SFR Page = 0
SFR Address = 0xCF; SFR Page = F
SFR Definition 22.7. SMB0ADM: SMBus0 Slave Address Mask
Bit76543210
Name
SLVM0[6:0] EHACK0
Type R/W R/W
Reset 11111110
Bit Name Function
7:1 SLVM0[6:0] SMBus0 Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM0[6:0] enables compari-
sons with the corresponding bit in SLV0[6:0]. Bits set to 0 are ignored (can be
either 0 or 1 in the incoming address).
0 EHACK0
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
SFR Definition 22.8. SMB1ADR: SMBus1 Slave Address
Bit76543210
Name
SLV1[6:0] GC1
Type R/W R/W
Reset 00000000
Bit Name Function
7:1 SLV1[6:0] SMBus1 Hardware Slave Address.
Defines the SMBus1 Slave Address(es) for automatic hardware acknowledge-
ment. Only address bits which have a 1 in the corresponding bit position in
SLVM1[6:0] are checked against the incoming address. This allows multiple
addresses to be recognized.
0GC1
General Call Address Enable.
When hardware address recognition is enabled (EHACK1 = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 224
SFR Address = 0xCE; SFR Page = F
SFR Definition 22.9. SMB1ADM: SMBus1 Slave Address Mask
Bit76543210
Name
SLVM1[6:0] EHACK1
Type R/W R/W
Reset 11111110
Bit Name Function
7:1 SLVM1[6:0] SMBus1 Slave Address Mask.
Defines which bits of register SMB1ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM1[6:0] enables compari-
sons with the corresponding bit in SLV1[6:0]. Bits set to 0 are ignored (can be
either 0 or 1 in the incoming address).
0 EHACK1
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
C8051F380/1/2/3/4/5/6/7/C
225 Rev. 1.5
22.4.5. Data Register
The SMBus Data register SMBnDAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SIn flag is set. Software should
not attempt to access the SMBnDAT register when the SMBus is enabled and the SIn flag is cleared to
logic 0, as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMBnDAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMBnDAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMBnDAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMBnDAT.
SFR Address = 0xC2; SFR Page = 0
SFR Definition 22.10. SMB0DAT: SMBus Data
Bit76543210
Name
SMB0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SMB0DAT[7:0] SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0
serial interface or a byte that has just been received on the SMBus0 serial inter-
face. The CPU can read from or write to this register whenever the SI0 serial inter-
rupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable
as long as the SI0 flag is set. When the SI0 flag is not set, the system may be in the
process of shifting data in/out and the CPU should not attempt to access this regis-
ter.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 226
SFR Address = 0xC2; SFR Page = F
SFR Definition 22.11. SMB1DAT: SMBus Data
Bit76543210
Name
SMB1DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SMB1DAT[7:0] SMBus1 Data.
The SMB1DAT register contains a byte of data to be transmitted on the SMBus1
serial interface or a byte that has just been received on the SMBus1 serial inter-
face. The CPU can read from or write to this register whenever the SI1 serial inter-
rupt flag (SMB1CN.0) is set to logic 1. The serial data in the register remains stable
as long as the SI1 flag is set. When the SI1 flag is not set, the system may be in the
process of shifting data in/out and the CPU should not attempt to access this regis-
ter.
C8051F380/1/2/3/4/5/6/7/C
227 Rev. 1.5
22.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. The position of the ACK interrupt when operating as a receiver depends on
whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
before the
ACK with hardware ACK generation disabled, and
after the ACK when hardware ACK generation is
enabled. As a transmitter, interrupts occur
after the ACK, regardless of whether hardware ACK generation
is enabled or not.
22.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. The interface will switch
to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 22.5
shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes
may be transmitted. Notice that all of the “data byte transferred” interrupts occur
after the ACK cycle in this
mode, regardless of whether hardware ACK generation is enabled.
Figure 22.5. Typical Master Write Sequence
A AAS W PData Byte Data ByteSLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 228
22.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt.
It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0-
DAT is written while an active Master Receiver. Figure 22.6 shows a typical master read sequence. Two
received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte
transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK
generation is enabled. The interrupt occurs
before the ACK with hardware ACK generation disabled, and
after the ACK when hardware ACK generation is enabled.
Figure 22.6. Typical Master Read Sequence
Data ByteData Byte A NAS R PSLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F380/1/2/3/4/5/6/7/C
229 Rev. 1.5
22.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt.
It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. The interface will switch to Slave Trans-
mitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 22.7 shows a typical slave write
sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that
the ‘data byte transferred’ interrupts occur at different places in the sequence, depending on whether hard-
ware ACK generation is enabled. The interrupt occurs
before the ACK with hardware ACK generation dis-
abled, and
after the ACK when hardware ACK generation is enabled.
Figure 22.7. Typical Slave Write Sequence
PWSLAS Data ByteData Byte A AA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 230
22.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters slave transmitter mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in slave transmitter mode). The interface exits slave transmitter mode after receiving a STOP.
The interface will switch to slave receiver mode if SMB0DAT is not written following a Slave Transmitter
interrupt. Figure 22.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though
any number of bytes may be transmitted. Notice that all of the “data byte transferred” interrupts occur
after
the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
Figure 22.8. Typical Slave Read Sequence
22.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 22.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 22.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the
typical responses; application-specific procedures are allowed as long as they conform to the SMBus
specification. Highlighted responses are allowed by hardware but do not conform to the SMBus specifica-
tion.
PRSLAS Data ByteData Byte A NA
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
C8051F380/1/2/3/4/5/6/7/C
231 Rev. 1.5
Table 22.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X
A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
00X1100
1100
000
A master data or address byte
was transmitted; NACK
received.
Set STA to restart transfer. 1 0 X 1110
Abort transfer.
01X —
001
A master data or address byte
was transmitted; ACK
received.
Load next data byte into SMB0-
DAT.
00X1100
End transfer with STOP. 0 1 X —
End transfer with STOP and start
another transfer.
11X —
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
0 0 X 1000
Master Receiver
1000 1 0 X
A master data byte was
received; ACK requested.
Acknowledge received byte;
Read SMB0DAT.
0 0 1 1000
Send NACK to indicate last byte,
and send STOP.
010 —
Send NACK to indicate last byte,
and send STOP followed by
START.
1101110
Send ACK followed by repeated
START.
1011110
Send NACK to indicate last byte,
and send repeated START.
1001110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 1 1100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 0 1100
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 232
Slave Transmitter
0100
000
A slave byte was transmitted;
NACK received.
No action required (expecting
STOP condition).
0 0 X 0001
001
A slave byte was transmitted;
ACK received.
Load SMB0DAT with next data
byte to transmit.
0 0 X 0100
01X
A Slave byte was transmitted;
error detected.
No action required (expecting
Master to end transfer).
0 0 X 0001
0101 0 X X
An illegal STOP or bus error
was detected while a Slave
Transmission was in progress.
Clear STO.
00X —
Slave Receiver
0010
10X
A slave address + R/W was
received; ACK requested.
If Write, Acknowledge received
address
0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK received address
0 0 1 0100
NACK received address. 0 0 0 —
11X
Lost arbitration as master;
slave address + R/W received;
ACK requested.
If Write, Acknowledge received
address
0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK received address
0 0 1 0100
NACK received address. 0 0 0 —
Reschedule failed transfer;
NACK received address.
1001110
0001
00X
A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
Clear STO.
00X —
11X
Lost arbitration while attempt-
ing a STOP.
No action required (transfer
complete/aborted).
000 —
0000 1 0 X
A slave byte was received;
ACK requested.
Acknowledge received byte;
Read SMB0DAT.
0 0 1 0000
NACK received byte. 0 0 0 —
Table 22.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F380/1/2/3/4/5/6/7/C
233 Rev. 1.5
Bus Error Condition
0010 0 1 X
Lost arbitration while attempt-
ing a repeated START.
Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0001 0 1 X
Lost arbitration due to a
detected STOP.
Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0000 1 1 X
Lost arbitration while transmit-
ting a data byte as master.
Abort failed transfer. 0 0 0 —
Reschedule failed transfer. 1 0 0 1110
Table 22.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X
A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
00X1100
1100
000
A master data or address byte
was transmitted; NACK
received.
Set STA to restart transfer. 1 0 X 1110
Abort transfer.
01X —
001
A master data or address byte
was transmitted; ACK
received.
Load next data byte into SMB0-
DAT.
00X1100
End transfer with STOP. 0 1 X —
End transfer with STOP and start
another transfer.
11X —
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
0 0 1 1000
Table 22.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 234
Master Receiver
1000
001
A master data byte was
received; ACK sent.
Set ACK for next data byte;
Read SMB0DAT.
0 0 1 1000
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
0 0 0 1000
Initiate repeated START. 1 0 0 1110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0 0 X 1100
000
A master data byte was
received; NACK sent (last
byte).
Read SMB0DAT; send STOP. 0 1 0 —
Read SMB0DAT; Send STOP
followed by START.
1101110
Initiate repeated START. 1 0 0 1110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0 0 X 1100
Slave Transmitter
0100
000
A slave byte was transmitted;
NACK received.
No action required (expecting
STOP condition).
0 0 X 0001
001
A slave byte was transmitted;
ACK received.
Load SMB0DAT with next data
byte to transmit.
0 0 X 0100
01X
A Slave byte was transmitted;
error detected.
No action required (expecting
Master to end transfer).
0 0 X 0001
0101 0 X X
An illegal STOP or bus error
was detected while a Slave
Transmission was in progress.
Clear STO.
00X —
Table 22.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F380/1/2/3/4/5/6/7/C
235 Rev. 1.5
Slave Receiver
0010
00X
A slave address + R/W was
received; ACK sent.
If Write, Set ACK for first data
byte.
0 0 1 0000
If Read, Load SMB0DAT with
data byte
0 0 X 0100
01X
Lost arbitration as master;
slave address + R/W received;
ACK sent.
If Write, Set ACK for first data
byte.
0 0 1 0000
If Read, Load SMB0DAT with
data byte
0 0 X 0100
Reschedule failed transfer 1 0 X 1110
0001
00X
A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
Clear STO.
00X —
01X
Lost arbitration while attempt-
ing a STOP.
No action required (transfer
complete/aborted).
000 —
0000 0 0 X A slave byte was received.
Set ACK for next data byte;
Read SMB0DAT.
0 0 1 0000
Set NACK for next data byte;
Read SMB0DAT.
0 0 0 0000
Bus Error Condition
0010 0 1 X
Lost arbitration while attempt-
ing a repeated START.
Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0001 0 1 X
Lost arbitration due to a
detected STOP.
Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0000 0 1 X
Lost arbitration while transmit-
ting a data byte as master.
Abort failed transfer. 0 0 X —
Reschedule failed transfer.
10X1110
Table 22.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
Mode
Values Read
Current SMbus State Typical Response Options
Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 236
23. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “23.1. Enhanced Baud Rate Generation” on page 237). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers.
Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Figure 23.1. UART0 Block Diagram
UART Baud
Rate Generator
RI
SCON
RI
TI
RB8
TB8
REN
MCE
SMODE
Tx Control
Tx Clock
Send
SBUF
(TX Shift)
Start
Data
Write to
SBUF
Crossbar
TX
Shift
Zero Detector
Tx IRQ
SET
QD
CLR
Stop Bit
TB8
SFR Bus
Serial
Port
Interrupt
TI
Port I/O
Rx Control
Start
Rx Clock
Load
SBUF
Shift 0x1FF RB8
Rx IRQ
Input Shift Register
(9 bits)
Load SBUF
Read
SBUF
SFR Bus
Crossbar
RX
SBUF
(RX Latch)
C8051F380/1/2/3/4/5/6/7/C
237 Rev. 1.5
23.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Figure 23.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “26.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 267). The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of
six sources: SYSCLK, SYSCLK/4, SYSCLK/12, SYSCLK/48, the external oscillator clock/8, or an external
input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 23.1-A and
Equation 23.1-B.
Equation 23.1. UART0 Baud Rate
Where T1
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “26. Timers” on page 263. A quick ref-
erence for typical baud rates and system clock frequencies is given in Table 23.1. The internal oscillator
may still generate the system clock when the external oscillator is driving Timer 1.
RX Timer
Start
Detected
Overflow
Overflow
TH1
TL1
TX Clock
2
RX Clock
2
Timer 1 UART
UARTBaudRate
1
2
---
T1_Overflow_Rate=
T1_Overflow_Rate
T1
CLK
256 TH1
–
---------------------------
=
A)
B)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 238
23.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 23.3.
Figure 23.3. UART Interconnect Diagram
23.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
Figure 23.4. 8-Bit UART Timing Diagram
OR
RS-232
C8051xxxx
RS-232
LEVEL
XLTR
TX
RX
C8051xxxx
RX
TX
MCU
RX
TX
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK
STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE
C8051F380/1/2/3/4/5/6/7/C
239 Rev. 1.5
23.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
Figure 23.5. 9-Bit UART Timing Diagram
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK
STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE
D8
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 240
23.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device
Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+
C8051F380/1/2/3/4/5/6/7/C
241 Rev. 1.5
SFR Address = 0x98; SFR Page = All Pages; Bit-Addressable
SFR Definition 23.1. SCON0: Serial Port 0 Control
Bit76543210
Name
S0MODE - MCE0 REN0 TB80 RB80 TI0 RI0
Type R/W R R/W R/W R/W R/W R/W R/W
Reset 01000000
Bit Name Function
7S0MODESerial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6 Unused Read = 1b, Write = don’t care.
5MCE0
Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4REN0
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
3TB80
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2RB80
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
1TI0
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0RI0
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 242
SFR Address = 0x99; SFR Page = All Pages
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer
Bit76543210
Name
SBUF0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Table 23.1. Timer Settings for Standard Baud Rates Using Internal Oscillator
Target
Baud
Rate (bps)
Actual
Baud
Rate (bps)
Baud
Rate
Error
Oscillator
Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale
select*
T1M Timer 1
Reload
Value (hex)
SYSCLK = 12 MHz
230400 230769 0.16% 52 SYSCLK XX 1 0xE6
115200 115385 0.16% 104 SYSCLK XX 1 0xCC
57600 57692 0.16% 208 SYSCLK XX 1 0x98
28800 28846 0.16% 416 SYSCLK XX 1 0x30
14400 14423 0.16% 832 SYSCLK / 4 01 0 0x98
9600 9615 0.16% 1248 SYSCLK / 4 01 0 0x64
2400 2404 0.16% 4992 SYSCLK / 12 00 0 0x30
1200 1202 0.16% 9984 SYSCLK / 48 10 0 0x98
SYSCLK = 24 MHz
230400 230769 0.16% 104 SYSCLK XX 1 0xCC
115200 115385 0.16% 208 SYSCLK XX 1 0x98
57600 57692 0.16% 416 SYSCLK XX 1 0x30
28800 28846 0.16% 832 SYSCLK / 4 01 0 0x98
14400 14423 0.16% 1664 SYSCLK / 4 01 0 0x30
9600 9615 0.16% 2496 SYSCLK / 12 00 0 0x98
2400 2404 0.16% 9984 SYSCLK / 48 10 0 0x98
1200 1202 0.16% 19968 SYSCLK / 48 10 0 0x30
SYSCLK = 48 MHz
230400 230769 0.16% 208 SYSCLK XX 1 0x98
115200 115385 0.16% 416 SYSCLK XX 1 0x30
57600 57692 0.16% 832 SYSCLK / 4 01 0 0x98
28800 28846 0.16% 1664 SYSCLK / 4 01 0 0x30
14400 14388 0.08% 3336 SYSCLK / 12 00 0 0x75
9600 9615 0.16% 4992 SYSCLK / 12 00 0 0x30
2400 2404 0.16% 19968 SYSCLK / 48 10 0 0x30
C8051F380/1/2/3/4/5/6/7/C
243 Rev. 1.5
Note: SCA1-SCA0 and T1M define the Timer Clock Source. X = Don’t care
Table 23.1. Timer Settings for Standard Baud Rates Using Internal Oscillator
Target
Baud
Rate (bps)
Actual
Baud
Rate (bps)
Baud
Rate
Error
Oscillator
Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale
select*
T1M Timer 1
Reload
Value (hex)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 244
24. UART1
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated
baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide
range of baud rates (details in Section “24.1. Baud Rate Generator” on page 245). A received data FIFO
allows UART1 to receive up to three data bytes before data is lost and an overflow occurs.
UART1 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON1, SBRLH1, and
SBRLL1), two are used for data formatting, control, and status functions (SCON1, SMOD1), and one is
used to send and receive data (SBUF1). The single SBUF1 location provides access to both the transmit
holding register and the receive FIFO.
Writes to SBUF1 always access the Transmit Holding Register.
Reads of SBUF1 always access the first byte of the Receive FIFO; it is not possible to read data
from the Transmit Holding Register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in
SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive
complete). Note that if additional bytes are available in the Receive FIFO, the RI1 bit cannot be cleared by
software.
Figure 24.1. UART1 Block Diagram
SBUF1
TX Holding
Register
RX FIFO
(3 Deep)
TX
Logic
RX
Logic
Write to SBUF1
Read of SBUF1
TX1
RX1
SMOD1
MCE1
S1PT1
S1PT0
PE1
S1DL1
S1DL0
XBE1
SBL1
Data Formatting
SCON1
OVR1
PERR1
THRE1
REN1
TBX1
RBX1
TI1
RI1
Control / Status
UART1
Interrupt
Timer (16-bit)
Pre-Scaler
(1, 4, 12, 48)
SYSCLK
SBRLH1 SBRLL1
Overflow
SBCON1
SB1RUN
SB1PS1
SB1PS0
EN
Baud Rate Generator
C8051F380/1/2/3/4/5/6/7/C
245 Rev. 1.5
24.1. Baud Rate Generator
The UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controller’s core clock
(SYSCLK), and has prescaler options of 1, 4, 12, or 48. The timer and prescaler options combined allow
for a wide selection of baud rates over many SYSCLK frequencies.
The baud rate generator is configured using three registers: SBCON1, SBRLH1, and SBRLL1. The
UART1 Baud Rate Generator Control Register (SBCON1, SFR Definition ) enables or disables the baud
rate generator, and selects the prescaler value for the timer. The baud rate generator must be enabled for
UART1 to function. Registers SBRLH1 and SBRLL1 contain a 16-bit reload value for the dedicated 16-bit
timer. The internal timer counts up from the reload value on every clock tick. On timer overflows (0xFFFF
to 0x0000), the timer is reloaded. For reliable UART operation, it is recommended that the UART baud rate
is not configured for baud rates faster than SYSCLK/16. The baud rate for UART1 is defined in
Equation 24.1.
Equation 24.1. UART1 Baud Rate
A quick reference for typical baud rates and system clock frequencies is given in Table 24.1.
Table 24.1. Baud Rate Generator Settings for Standard Baud Rates
Target Baud
Rate (bps)
Actual Baud
Rate (bps)
Baud Rate
Error
Oscillator
Divide
Factor
SB1PS[1:0]
(Prescaler Bits)
Reload Value in
SBRLH1:SBRLL1
SYSCLK = 12 MHz
230400 230769 0.16% 52 11 0xFFE6
115200 115385 0.16% 104 11 0xFFCC
57600 57692 0.16% 208 11 0xFF98
28800 28846 0.16% 416 11 0xFF30
14400 14388 0.08% 834 11 0xFE5F
9600 9600 0.0% 1250 11 0xFD8F
2400 2400 0.0% 5000 11 0xF63C
1200 1200 0.0% 10000 11 0xEC78
SYSCLK = 24 MHz
230400 230769 0.16% 104 11 0xFFCC
115200 115385 0.16% 208 11 0xFF98
57600 57692 0.16% 416 11 0xFF30
28800 28777 0.08% 834 11 0xFE5F
14400 14406 0.04% 1666 11 0xFCBF
9600 9600 0.0% 2500 11 0xFB1E
2400 2400 0.0% 10000 11 0xEC78
1200 1200 0.0% 20000 11 0xD8F0
SYSCLK = 48 MHz
230400 230769 0.16% 208 11 0xFF98
115200 115385 0.16% 416 11 0xFF30
57600 57554 0.08% 834 11 0xFE5F
28800 28812 0.04% 1666 11 0xFCBF
14400 14397 0.02% 3334 11 0xF97D
9600 9600 0.0% 5000 11 0xF63C
2400 2400 0.0% 20000 11 0xD8F0
1200 1200 0.0% 40000 11 0xB1E0
Baud Rate
SYSCLK
65536 (SBRLH1:SBRLL1)
–
------------------------------------------------------------------------------
1
2
---
1
Prescaler
-------------------------
=
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 246
24.2. Data Format
UART1 has a number of available options for data formatting. Data transfers begin with a start bit (logic
low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two
stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the
data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The
stop bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor
communication mode is available for implementing networked UART buses. All of the data formatting
options can be configured using the SMOD1 register, shown in SFR Definition . Figure 24.2 shows the tim-
ing for a UART1 transaction without parity or an extra bit enabled. Figure 24.3 shows the timing for a
UART1 transaction with parity enabled (PE1 = 1). Figure 24.4 is an example of a UART1 transaction when
the extra bit is enabled (XBE1 = 1). Note that the extra bit feature is not available when parity is enabled,
and the second stop bit is only an option for data lengths of 6, 7, or 8 bits.
Figure 24.2. UART1 Timing Without Parity or Extra Bit
Figure 24.3. UART1 Timing With Parity
Figure 24.4. UART1 Timing With Extra Bit
D
1
D
0
D
N-2
D
N-1
START
BIT
MARK
STOP
BIT 1
BIT TIMES
SPACE
N bits; N = 5, 6, 7, or 8
STOP
BIT 2
Optional
D
1
D
0
D
N-2
D
N-1
PARITY
START
BIT
MARK
STOP
BIT 1
BIT TIMES
SPACE
N bits; N = 5, 6, 7, or 8
STOP
BIT 2
Optional
D
1
D
0
D
N-2
D
N-1
EXTRA
START
BIT
MARK
STOP
BIT 1
BIT TIMES
SPACE
N bits; N = 5, 6, 7, or 8
STOP
BIT 2
Optional
C8051F380/1/2/3/4/5/6/7/C
247 Rev. 1.5
24.3. Configuration and Operation
UART1 provides standard asynchronous, full duplex communication. It can operate in a point-to-point
serial communications application, or as a node on a multi-processor serial interface. To operate in a point-
to-point application, where there are only two devices on the serial bus, the MCE1 bit in SMOD1 should be
cleared to 0. For operation as part of a multi-processor communications bus, the MCE1 and XBE1 bits
should both be set to 1. In both types of applications, data is transmitted from the microcontroller on the
TX1 pin, and received on the RX1 pin. The TX1 and RX1 pins are configured using the crossbar and the
Port I/O registers, as detailed in Section “20. Port Input/Output” on page 157.
In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX)
input of the other device, either directly or through a bus transceiver, as shown in Figure 24.5.
Figure 24.5. Typical UART Interconnect Diagram
24.3.1. Data Transmission
Data transmission is double-buffered, and begins when software writes a data byte to the SBUF1 register.
Writing to SBUF1 places data in the Transmit Holding Register, and the Transmit Holding Register Empty
flag (THRE1) will be cleared to 0. If the UARTs shift register is empty (i.e. no transmission is in progress)
the data will be placed in the shift register, and the THRE1 bit will be set to 1. If a transmission is in prog-
ress, the data will remain in the Transmit Holding Register until the current transmission is complete. The
TI1 Transmit Interrupt Flag (SCON1.1) will be set at the end of any transmission (the beginning of the stop-
bit time). If enabled, an interrupt will occur when TI1 is set.
If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the value of the
TBX1 (SCON1.3) bit will be sent in the extra bit position. When the parity function is enabled (PE1 = 1),
hardware will generate the parity bit according to the selected parity type (selected with S1PT[1:0]), and
append it to the data field. Note: when parity is enabled, the extra bit function is not available.
24.3.2. Data Reception
Data reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the
stop bit is received, the data byte will be stored in the receive FIFO if the following conditions are met: the
receive FIFO (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. In the event that the
receive FIFO is full, the incoming byte will be lost, and a Receive FIFO Overrun Error will be generated
(OVR1 in register SCON1 will be set to logic 1). If the stop bit(s) were logic 0, the incoming data will not be
stored in the receive FIFO. If the reception conditions are met, the data is stored in the receive FIFO, and
the RI1 flag will be set. Note: when MCE1 = 1, RI1 will only be set if the extra bit was equal to 1. Data can
be read from the receive FIFO by reading the SBUF1 register. The SBUF1 register represents the oldest
byte in the FIFO. After SBUF1 is read, the next byte in the FIFO is immediately loaded into SBUF1, and
space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI1
is set. RI1 can only be cleared to '0' by software when there is no more information in the FIFO. The rec-
ommended procedure to empty the FIFO contents is:
OR
RS-232
C8051Fxxx
RS-232
LEVEL
TRANSLATOR
TX
RX
C8051Fxxx
RX
TX
MCU
RX
TX
PC
COM Port
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 248
1. Clear RI1 to 0
2. Read SBUF1
3. Check RI1, and repeat at Step 1 if RI1 is set to 1.
If the extra bit function is enabled (XBE1 = 1) and the parity function is disabled (PE1 = 0), the extra bit for
the oldest byte in the FIFO can be read from the RBX1 bit (SCON1.2). If the extra bit function is not
enabled, the value of the stop bit for the oldest FIFO byte will be presented in RBX1. When the parity func-
tion is enabled (PE1 = 1), hardware will check the received parity bit against the selected parity type
(selected with S1PT[1:0]) when receiving data. If a byte with parity error is received, the PERR1 flag will be
set to 1. This flag must be cleared by software. Note: when parity is enabled, the extra bit function is not
available.
24.3.3. Multiprocessor Communications
UART1 supports multiprocessor communication between a master processor and one or more slave pro-
cessors by special use of the extra data bit. When a master processor wants to transmit to one or more
slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that
its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0.
Setting the MCE1 bit (SMOD1.7) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the extra bit is logic 1 (RBX1 = 1) signifying an
address byte has been received. In the UART interrupt handler, software will compare the received
address with the slave's own assigned address. If the addresses match, the slave will clear its MCE1 bit to
enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their
MCE1 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring
the data. Once the entire message is received, the addressed slave resets its MCE1 bit to ignore all trans-
missions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device
Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+
C8051F380/1/2/3/4/5/6/7/C
249 Rev. 1.5
SFR Address = 0xD2; SFR Page = All Pages
SFR Definition 24.1. SCON1: UART1 Control
Bit76543210
Name
OVR1 PERR1 THRE1 REN1 TBX1 RBX1 TI1 RI1
Type R/W R/W R R/W R/W R/W R/W R/W
Reset 00100000
Bit Name Function
7OVR1Receive FIFO Overrun Flag.
This bit indicates a receive FIFO overrun condition, where an incoming character is discarded
due to a full FIFO. This bit must be cleared to 0 by software.
0: Receive FIFO Overrun has not occurred.
1: Receive FIFO Overrun has occurred.
6 PERR1
Parity Error Flag.
When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1 when the
parity of the oldest byte in the FIFO does not match the selected Parity Type. This bit must be
cleared to 0 by software.
0: Parity Error has not occurred.
1: Parity Error has occurred.
5 THRE1
Transmit Holding Register Empty Flag.
0: Transmit Holding Register not Empty - do not write to SBUF1.
1: Transmit Holding Register Empty - it is safe to write to SBUF1.
4REN1
Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read from the
receive FIFO.
0: UART1 reception disabled.
1: UART1 reception enabled.
3 TBX1
Extra Transmission Bit.
The logic level of this bit will be assigned to the extra transmission bit when XBE1 = 1. This bit is
not used when Parity is enabled.
2 RBX1
Extra Receive Bit.
RBX1 is assigned the value of the extra bit when XBE1 = 1. If XBE1 is cleared to 0, RBX1 is
assigned the logic level of the first stop bit. This bit is not valid when Parity is enabled.
1TI1
Transmit Interrupt Flag.
Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit. When
the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt
service routine. This bit must be cleared manually by software.
0RI1
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART1 (set at the STOP bit sam-
pling time). When the UART1 interrupt is enabled, setting this bit to 1 causes the CPU to vector
to the UART1 interrupt service routine. This bit must be cleared manually by software. Note that
RI1 will remain set to '1' as long as there is still data in the UART FIFO. After the last byte has
been shifted from the FIFO to SBUF1, RI1 can be cleared.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 250
SFR Address = 0xE5; SFR Page = All Pages
SFR Definition 24.2. SMOD1: UART1 Mode
Bit76543210
Name
MCE1 S1PT[1:0] PE1 S1DL[1:0] XBE1 SBL1
Type
R/W R/W R/W R/W R/W R/W
Reset
00001100
Bit Name Function
7MCE1
Multiprocessor Communication Enable.
0: RI will be activated if stop bit(s) are 1.
1: RI will be activated if stop bit(s) and extra bit are 1 (extra bit must be enabled using
XBE1).
Note: This function is not available when hardware parity is enabled.
6:5 S1PT[1:0]
Parity Type Bits.
00: Odd
01: Even
10: Mark
11: Space
4 PE1
Parity Enable.
This bit activates hardware parity generation and checking. The parity type is selected
by bits S1PT1-0 when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
3:2 S1DL[1:0]
Data Length.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
1 XBE1
Extra Bit Enable.
When enabled, the value of TBX1 will be appended to the data field.
0: Extra Bit Disabled.
1: Extra Bit Enabled.
0SBL1
Stop Bit Length.
0: Short—Stop bit is active for one bit time.
1: Long—Stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
C8051F380/1/2/3/4/5/6/7/C
251 Rev. 1.5
SFR Address = 0xD3; SFR Page = All Pages
SFR Definition 24.3. SBUF1: UART1 Data Buffer
Bit76543210
Name
SBUF1[7:0]
Type R/W
Reset 00000000
Bit Name Description Write Read
7:0 SBUF1[7:0] Serial Data Buffer Bits.
This SFR is used to both send
data from the UART and to
read received data from the
UART1 receive FIFO.
Writing a byte to SBUF1
initiates the transmission.
When data is written to
SBUF1, it first goes to the
Transmit Holding Register,
where it is held for serial
transmission. When the
transmit shift register is
available, data is trans-
ferred into the shift regis-
ter, and SBUF1 may be
written again.
Reading SBUF1 retrieves
data from the receive
FIFO. When read, the old-
est byte in the receive
FIFO is returned, and
removed from the FIFO.
Up to three bytes may be
held in the FIFO. If there
are additional bytes avail-
able in the FIFO, the RI1
bit will remain at logic 1,
even after being cleared
by software.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 252
SFR Address = 0xAC; SFR Page = All Pages
SFR Address = 0xB5; SFR Page = All Pages
SFR Definition 24.4. SBCON1: UART1 Baud Rate Generator Control
Bit76543210
Name
SB1RUN SB1PS[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 Reserved Read = 0b. Must Write 0b.
6 SB1RUN
Baud Rate Generator Enable.
0: Baud Rate Generator is disabled. UART1 will not function.
1: Baud Rate Generator is enabled.
5:2 Reserved Read = 0000b. Must Write 0000b.
1:0 SB1PS[1:0]
Baud Rate Prescaler Select.
00: Prescaler = 12
01: Prescaler = 4
10: Prescaler = 48
11: Prescaler = 1
SFR Definition 24.5. SBRLH1: UART1 Baud Rate Generator High Byte
Bit76543210
Name
SBRLH1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBRLH1[7:0]
UART1 Baud Rate Reload High Bits.
High Byte of reload value for UART1 Baud Rate Generator.
C8051F380/1/2/3/4/5/6/7/C
253 Rev. 1.5
SFR Address = 0xB4; SFR Page = All Pages
SFR Definition 24.6. SBRLL1: UART1 Baud Rate Generator Low Byte
Bit76543210
Name
SBRLL1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBRLL1[7:0] UART1 Baud Rate Reload Low Bits.
Low Byte of reload value for UART1 Baud Rate Generator.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 254
25. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 25.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
01234567
Shift Register
SPI CONTROL LOGIC
SPI0CKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CFG SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL
SLVSEL
NSSMD1
NSSMD0
SPIBSY
MSTEN
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
TXBMT
SPIEN
C8051F380/1/2/3/4/5/6/7/C
255 Rev. 1.5
25.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
25.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
25.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
25.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
25.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-
point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 25.2, Figure 25.3, and Figure 25.4 for typical connection diagrams of the various operational
modes.
Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “20. Port Input/Output” on page 157 for general purpose
port I/O and crossbar information.
25.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 256
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSS-
MD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-mas-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 25.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 25.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 25.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
Figure 25.2. Multiple-Master Mode Connection Diagram
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Master
Device 2
Master
Device 1
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS
GPIO
NSS
GPIO
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
C8051F380/1/2/3/4/5/6/7/C
257 Rev. 1.5
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
25.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 25.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 25.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS NSS
GPIO
Slave
Device
MOSI
MISO
SCK
NSS
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 258
25.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
25.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 25.5. For slave mode, the clock and
data relationships are shown in Figure 25.6 and Figure 25.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 25.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
C8051F380/1/2/3/4/5/6/7/C
259 Rev. 1.5
Figure 25.5. Master Mode Data/Clock Timing
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO/MOSI
NSS (Must Remain High
in Multi-Master Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 260
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1)
25.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
C8051F380/1/2/3/4/5/6/7/C
261 Rev. 1.5
SFR Address = 0xA1; SFR Page = All Pages
SFR Definition 25.1. SPI0CFG: SPI0 Configuration
Bit7654321 0
Name
SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT
Type R R/W R/W R/W R R R R
Reset 0000011 1
Bit Name Function
7 SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6 MSTEN
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
5 CKPHA
SPI0 Clock Phase.
0: Data centered on first edge of SCK period.
*
1: Data centered on second edge of SCK period.
*
4CKPOLSPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3 SLVSEL
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2 NSSIN
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1SRMT
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0 RXBMT
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 25.1 for timing parameters.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 262
SFR Address = 0xF8; SFR Page = All Pages; Bit-Addressable
SFR Definition 25.2. SPI0CN: SPI0 Control
Bit7654321 0
Name
SPIF WCOL MODF RXOVRN NSSMD[1:0] TXBMT SPIEN
Type R/W R/W R/W R/W R/W R R/W
Reset 0000011 0
Bit Name Function
7 SPIF SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6WCOL
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
5MODF
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
4 RXOVRN
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
3:2 NSSMD[1:0]
Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 25.2 and Section 25.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1 TXBMT
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0 SPIEN
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
C8051F380/1/2/3/4/5/6/7/C
263 Rev. 1.5
SFR Address = 0xA2; SFR Page = All Pages
SFR Address = 0xA3; SFR Page = All Pages
SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate
Bit7654321 0
Name
SCR[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SCR[7:0] SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where
SYSCLK is
the system clock frequency and
SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0
SPI0CKR 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
SFR Definition 25.4. SPI0DAT: SPI0 Data
Bit7654321 0
Name
SPI0DAT[7:0]
Type R/W
Reset 0000000 0
Bit Name Function
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
f
SCK
SYSCLK
2 SPI0CKR[7:0] 1+
-------------------------------------------------------------=
f
SCK
2000000
241+
---------------------------=
f
SCK
200kHz=
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 264
Figure 25.8. SPI Master Timing (CKPHA = 0)
Figure 25.9. SPI Master Timing (CKPHA = 1)
SCK*
T
MCKH
T
MCKL
MOSI
T
MIS
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIH
SCK*
T
MCKH
T
MCKL
MISO
T
MIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIS
C8051F380/1/2/3/4/5/6/7/C
265 Rev. 1.5
Figure 25.10. SPI Slave Timing (CKPHA = 0)
Figure 25.11. SPI Slave Timing (CKPHA = 1)
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SEZ
T
SDZ
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SEZ
T
SDZ
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 266
Table 25.1. SPI Slave Timing Parameters
Parameter Description Min Max Units
Master Mode Timing
(See Figure 25.8 and Figure 25.9)
T
MCKH
SCK High Time 1 x T
SYSCLK
—ns
T
MCKL
SCK Low Time 1 x T
SYSCLK
—ns
T
MIS
MISO Valid to SCK Shift Edge 1 x T
SYSCLK
+ 20 — ns
T
MIH
SCK Shift Edge to MISO Change 0 — ns
Slave Mode Timing (See Figure 25.10 and Figure 25.11)
T
SE
NSS Falling to First SCK Edge 2 x T
SYSCLK
—ns
T
SD
Last SCK Edge to NSS Rising 2 x T
SYSCLK
—ns
T
SEZ
NSS Falling to MISO Valid — 4 x T
SYSCLK
ns
T
SDZ
NSS Rising to MISO High-Z — 4 x T
SYSCLK
ns
T
CKH
SCK High Time 5 x T
SYSCLK
—ns
T
CKL
SCK Low Time 5 x T
SYSCLK
—ns
T
SIS
MOSI Valid to SCK Sample Edge 2 x T
SYSCLK
—ns
T
SIH
SCK Sample Edge to MOSI Change 2 x T
SYSCLK
—ns
T
SOH
SCK Shift Edge to MISO Change — 4 x T
SYSCLK
ns
T
SLH
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6xT
SYSCLK
8xT
SYSCLK
ns
Note: T
SYSCLK
is equal to one period of the device system clock (SYSCLK).
C8051F380/1/2/3/4/5/6/7/C
267 Rev. 1.5
26. Timers
Each MCU includes six counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and four are 16-bit auto-reload timer for use with the SMBus or for general purpose use.
These timers can be used to measure time intervals, count external events and generate periodic interrupt
requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2, 3,
4, and 5 offer 16-bit and split 8-bit timer functionality with auto-reload.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M
–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 26.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2, 3, 4,
and 5 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock
source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Timer 0 and Timer 1 Modes: Timer 2, 3, 4, and 5 Modes:
13-bit counter/timer
16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0 only)
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 268
SFR Address = 0x8E; SFR Page = All Pages
SFR Definition 26.1. CKCON: Clock Control
Bit76543210
Name
T3MH T3ML T2MH T2ML T1M T0M SCA[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7T3MHTimer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6T3ML
Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5T2MH
Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4T2ML
Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3T1
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2T0
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0]
Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
C8051F380/1/2/3/4/5/6/7/C
269 Rev. 1.5
SFR Address = 0xE4; SFR Page = F
SFR Definition 26.2. CKCON1: Clock Control 1
Bit76543210
Name
T5MH T5ML T4MH T4ML
Type RRRRR/WR/WR/WR/W
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b; Write = don’t care
3T5MH
Timer 5 High Byte Clock Select.
Selects the clock supplied to the Timer 5 high byte (split 8-bit timer mode only).
0: Timer 5 high byte uses the clock defined by the T5XCLK bit in TMR5CN.
1: Timer 5 high byte uses the system clock.
2T5ML
Timer 5 Low Byte Clock Select.
Selects the clock supplied to Timer 5. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 5 low byte uses the clock defined by the T5XCLK bit in TMR5CN.
1: Timer 5 low byte uses the system clock.
1T4MH
Timer 4 High Byte Clock Select.
Selects the clock supplied to the Timer 4 high byte (split 8-bit timer mode only).
0: Timer 4 high byte uses the clock defined by the T4XCLK bit in TMR4CN.
1: Timer 4 high byte uses the system clock.
0T4ML
Timer 4 Low Byte Clock Select.
Selects the clock supplied to Timer 4. If Timer 4 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 4 low byte uses the clock defined by the T4XCLK bit in TMR4CN.
1: Timer 4 low byte uses the system clock.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 270
26.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter; Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register. Both counter/timers operate
in one of four primary modes selected by setting the Mode Select bits T1M1
–T0M0 in the Counter/Timer
Mode register (TMOD). Each timer can be configured independently. Each operating mode is described
below.
26.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4
–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 in TCON is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit in the TMOD register selects the counter/timer's clock source. When C/T0 is set to logic 1,
high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“20.1. Priority Crossbar Decoder” on page 158 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit in register CKCON. When T0M is set, Timer 0
is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the
Clock Scale bits in CKCON (see SFR Definition 26.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or the
input signal INT0
is active as defined by bit IN0PL in register IT01CF. Setting GATE0 to 1 allows the timer
to be controlled by the external input signal INT0
, facilitating pulse width measurements
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1
is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF.
TR0 GATE0 INT0 Counter/Timer
0 X X Disabled
1 0 X Enabled
1 1 0 Disabled
1 1 1 Enabled
Note: X = Don't Care
C8051F380/1/2/3/4/5/6/7/C
271 Rev. 1.5
Figure 26.1. T0 Mode 0 Block Diagram
26.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
26.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0
is active as defined by bit IN0PL in register IT01CF (see SFR Definition 16.7 for details on the
external input signals INT0
and INT1).
TCLK
TL0
(5 bits)
TH0
(8 bits)
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TR0
0
1
0
1
SYSCLK
Pre-scaled Clock
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
GATE0
INT0
T0
Crossbar
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
IN0PL
XOR
T0M
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 272
Figure 26.2. T0 Mode 2 Block Diagram
26.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus con-
trols the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals.
While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run
Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for
Mode 3.
TCLK
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TL0
(8 bits)
Reload
TH0
(8 bits)
0
1
0
1
SYSCLK
Pre-scaled Clock
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
TR0
GATE0
IN0PL
XOR
INT0
T0
Crossbar
T0M
C8051F380/1/2/3/4/5/6/7/C
273 Rev. 1.5
Figure 26.3. T0 Mode 3 Block Diagram
TL0
(8 bits)
TMOD
0
1
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
Interrupt
0
1
SYSCLK
Pre-scaled Clock
TR1
TH0
(8 bits)
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TR0
GATE0
IN0PL
XOR
INT0
T0
Crossbar
T0M
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 274
SFR Address = 0x88; SFR Page = All Pages; Bit-Addressable
SFR Definition 26.3. TCON: Timer Control
Bit76543210
Name
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF1 Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6TR1
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5 TF0
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4TR0
Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3IE1
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2IT1
Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1
is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 16.7).
0: INT1
is level triggered.
1: INT1
is edge triggered.
1IE0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
0IT0
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0
is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 16.7).
0: INT0
is level triggered.
1: INT0
is edge triggered.
C8051F380/1/2/3/4/5/6/7/C
275 Rev. 1.5
SFR Address = 0x89; SFR Page = All Pages
SFR Definition 26.4. TMOD: Timer Mode
Bit76543210
Name
GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7GATE1Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1
is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 16.7).
6C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4 T1M[1:0]
Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3GATE0
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0
is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 16.7).
2C/T0
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0 T0M[1:0]
Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 276
SFR Address = 0x8A; SFR Page = All Pages
SFR Address = 0x8B; SFR Page = All Pages
SFR Definition 26.5. TL0: Timer 0 Low Byte
Bit76543210
Name
TL0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL0[7:0] Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 26.6. TL1: Timer 1 Low Byte
Bit76543210
Name
TL1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL1[7:0] Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
C8051F380/1/2/3/4/5/6/7/C
277 Rev. 1.5
SFR Address = 0x8C; SFR Page = All Pages
SFR Address = 0x8D; SFR Page = All Pages
SFR Definition 26.7. TH0: Timer 0 High Byte
Bit76543210
Name
TH0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH0[7:0] Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 26.8. TH1: Timer 1 High Byte
Bit76543210
Name
TH1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH1[7:0] Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 278
26.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture
mode, or Low-Frequency Oscillator (LFO) Falling Edge capture mode. The Timer 2 operation mode is
defined by the T2SPLIT (TMR2CN.3), T2CE (TMR2CN.4) bits, and T2CSS (TMR2CN.1) bits.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
26.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 26.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
Figure 26.4. Timer 2 16-Bit Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH
Reload
TCLK
0
1
TR2
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
0
1
T2XCLK
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TL2
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F380/1/2/3/4/5/6/7/C
279 Rev. 1.5
26.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 26.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
Figure 26.5. Timer 2 8-Bit Mode Block Diagram
26.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge
When T2CE = 1, Timer 2 will operate in one of two special capture modes. The capture event can be
selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Falling
Edge capture, using the T2CSS bit. The USB SOF capture mode can be used to calibrate the system clock
or external oscillator against the known USB host SOF clock. The LFO falling-edge capture mode can be
used to calibrate the internal Low-Frequency Oscillator against the internal High-Frequency Oscillator or
an external clock source. When T2SPLIT = 0, Timer 2 counts up and overflows from 0xFFFF to 0x0000.
T2MH T2XCLK TMR2H Clock Source T2ML T2XCLK TMR2L Clock Source
0 0 SYSCLK / 12 0 0 SYSCLK / 12
0 1 External Clock / 8 0 1 External Clock / 8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1
TR2
External Clock / 8
SYSCLK / 12
0
1
T2XCLK
1
0
TMR2H
TMR2RLH
Reload
Reload
TCLK
TMR2L
TMR2RLL
Interrupt
TMR2CN
T2SPLIT
TF2CEN
TF2LEN
TF2L
TF2H
T2XCLK
TR2
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 280
Each time a capture event is received, the contents of the Timer 2 registers (TMR2H:TMR2L) are latched
into the Timer 2 Reload registers (TMR2RLH:TMR2RLL). A Timer 2 interrupt is generated if enabled.
Figure 26.6. Timer 2 Capture Mode (T2SPLIT = 0)
When T2SPLIT = 1, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.
External Clock / 8
SYSCLK / 12
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH
TCLK
0
1
TR2
0
1
Interrupt
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
Capture
USB Start-of-Frame (SOF)
Enable
TMR2CN
T
F
2
H
T
F
2
L
T
2
X
C
L
K
T
2
C
S
S
T
R
2
T
F
2
L
E
N
T
2
C
E
T
2
S
P
L
I
T
0
1
T2CSS
Low-Frequency Oscillator
Falling Edge
To ADC,
SMBus
To SMBus
TL2
Overflow
C8051F380/1/2/3/4/5/6/7/C
281 Rev. 1.5
Figure 26.7. Timer 2 Capture Mode (T2SPLIT = 0)
SYSCLK
TCLK
0
1
TR2
External Clock / 8
SYSCLK / 12
0
1
1
0
TMR2H
TMR2RLH
TCLK
TMR2L
TMR2RLL
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR2CN
T
F
2
H
T
F
2
L
T
2
X
C
L
K
T
2
C
S
S
T
R
2
T
F
2
L
E
N
T
2
C
E
T
2
S
P
L
I
T
Capture
Enable
Capture
Interrupt
USB Start-of-Frame (SOF)
Low-Frequency Oscillator
Falling Edge
0
1
T2CSS
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 282
SFR Address = 0xC8; SFR Page = 0; Bit-Addressable
SFR Definition 26.9. TMR2CN: Timer 2 Control
Bit76543210
Name
TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2CSS T2XCLK
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF2H Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware.
6 TF2L
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5 TF2LEN
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
4TF2CEN
Timer 2 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 2 Low-Frequency Oscillator Capture Mode. If
TF2CEN is set and Timer 2 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL.
3 T2SPLIT
Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
2TR2
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1T2CSS
Timer 2 Capture Source Select.
This bit selects the source of a capture event when bit T2CE is set to 1.
0: Capture source is USB SOF event.
1: Capture source is falling edge of Low-Frequency Oscillator.
0T2XCLK
Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between
the external clock and the system clock for either timer.
0: Timer 2 clock is the system clock divided by 12.
1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F380/1/2/3/4/5/6/7/C
283 Rev. 1.5
SFR Address = 0xCA; SFR Page = 0
SFR Address = 0xCB; SFR Page = 0
SFR Address = 0xCC; SFR Page = 0
SFR Definition 26.10. TMR2RLL: Timer 2 Reload Register Low Byte
Bit76543210
Name
TMR2RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 26.11. TMR2RLH: Timer 2 Reload Register High Byte
Bit76543210
Name
TMR2RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
SFR Definition 26.12. TMR2L: Timer 2 Low Byte
Bit76543210
Name
TMR2L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 284
SFR Address = 0xCD; SFR Page = 0
SFR Definition 26.13. TMR2H Timer 2 High Byte
Bit76543210
Name
TMR2H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 281
26.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture
mode, or Low-Frequency Oscillator (LFO) Rising Edge capture mode. The Timer 3 operation mode is
defined by the T3SPLIT (TMR3CN.3), T3CE (TMR3CN.4) bits, and T3CSS (TMR3CN.1) bits.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
26.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 26.8,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow from 0xFF to 0x00.
Figure 26.8. Timer 3 16-Bit Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
TMR3L TMR3H
TMR3RLL TMR3RLH
Reload
TCLK
0
1
TR3
TMR3CN
T3SPLIT
T3CSS
T3CE
TF3L
TF3H
T3XCLK
TR3
0
1
T3XCLK
Interrupt
TF3LEN
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F380/1/2/3/4/5/6/7/C
282 Rev. 1.5
26.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is 1 and T3CE = 0, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 26.9. TMR3RLL holds the reload value for TMR3L;
TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H.
TMR3L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 26.9. Timer 3 8-Bit Mode Block Diagram
26.3.3. Timer 3 Capture Modes: USB Start-of-Frame or LFO Falling Edge
When T3CE = 1, Timer 3 will operate in one of two special capture modes. The capture event can be
selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Falling
Edge capture, using the T3CSS bit. The USB SOF capture mode can be used to calibrate the system clock
or external oscillator against the known USB host SOF clock. The LFO falling-edge capture mode can be
used to calibrate the internal Low-Frequency Oscillator against the internal High-Frequency Oscillator or
an external clock source. When T3SPLIT = 0, Timer 3 counts up and overflows from 0xFFFF to 0x0000.
Each time a capture event is received, the contents of the Timer 3 registers (TMR3H:TMR3L) are latched
into the Timer 3 Reload registers (TMR3RLH:TMR3RLL). A Timer 3 interrupt is generated if enabled.
T3MH T3XCLK TMR3H Clock Source T3ML T3XCLK TMR3L Clock Source
0 0 SYSCLK / 12 0 0 SYSCLK / 12
0 1 External Clock / 8 0 1 External Clock / 8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1
TR3
External Clock / 8
SYSCLK / 12
0
1
T3XCLK
1
0
TMR3H
TMR3RLH
Reload
Reload
TCLK
TMR3L
TMR3RLL
Interrupt
TMR3CN
T3SPLIT
T3CSS
T3CE
TF3LEN
TF3L
TF3H
T3XCLK
TR3
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
To ADC
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 283
Figure 26.10. Timer 3 Capture Mode (T3SPLIT = 0)
When T3SPLIT = 1, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
External Clock / 8
SYSCLK / 12
SYSCLK
TMR3L TMR3H
TMR3RLL TMR3RLH
TCLK
0
1
TR3
0
1
Interrupt
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
Capture
Enable
TMR3CN
T
F
3
H
T
F
3
L
T
3
X
C
L
K
T
3
C
S
S
T
R
3
T
F
3
L
E
N
T
3
C
E
T
3
S
P
L
I
T
USB Start-of-Frame (SOF)
0
1
T3CSS
Low-Frequency Oscillator
Falling Edge
C8051F380/1/2/3/4/5/6/7/C
284 Rev. 1.5
Figure 26.11. Timer 3 Capture Mode (T3SPLIT = 0)
SYSCLK
TCLK
0
1
TR3
External Clock / 8
SYSCLK / 12
0
1
1
0
TMR3H
TMR3RLH
TCLK
TMR3L
TMR3RLL
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR3CN
T
F
3
H
T
F
3
L
T
3
X
C
L
K
T
3
C
S
S
T
R
3
T
F
3
L
E
N
T
3
C
E
T
3
S
P
L
I
T
Capture
Enable
Capture
Interrupt
USB Start-of-Frame (SOF)
Low-Frequency Oscillator
Falling Edge
0
1
T3CSS
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 285
SFR Address = 0x91; SFR Page = 0
SFR Definition 26.14. TMR3CN: Timer 3 Control
Bit76543210
Name
TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3CSS T3XCLK
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF3H Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6 TF3L
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5 TF3LEN
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4TF3CEN
Timer 3 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Low-Frequency Oscillator Capture Mode. If
TF3CEN is set and Timer 3 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL.
3 T3SPLIT
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
2TR3
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
1T3CSS
Timer 3 Capture Source Select.
This bit selects the source of a capture event when bit T2CE is set to 1.
0: Capture source is USB SOF event.
1: Capture source is falling edge of Low-Frequency Oscillator.
0T3XCLK
Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. However, the Timer 3 Clock
Select bits (T3MH and T3ML in register CKCON) may still be used to select between
the external clock and the system clock for either timer.
0: Timer 3 clock is the system clock divided by 12.
1: Timer 3 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F380/1/2/3/4/5/6/7/C
286 Rev. 1.5
SFR Address = 0x92; SFR Page = 0
SFR Address = 0x93; SFR Page = 0
SFR Address = 0x94; SFR Page = 0
SFR Definition 26.15. TMR3RLL: Timer 3 Reload Register Low Byte
Bit76543210
Name
TMR3RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 26.16. TMR3RLH: Timer 3 Reload Register High Byte
Bit76543210
Name
TMR3RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
SFR Definition 26.17. TMR3L: Timer 3 Low Byte
Bit76543210
Name
TMR3L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 287
SFR Address = 0x95; SFR Page = 0
SFR Definition 26.18. TMR3H Timer 3 High Byte
Bit76543210
Name
TMR3H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 288
26.4. Timer 4
Timer 4 is a 16-bit timer formed by two 8-bit SFRs: TMR4L (low byte) and TMR4H (high byte). Timer 4 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T4SPLIT bit (TMR4CN.3) defines
Timer 4 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system
clock.
26.4.1. 16-bit Timer with Auto-Reload
When T4SPLIT (TMR4CN.3) is zero, Timer 4 operates as a 16-bit timer with auto-reload. Timer 4 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 4
reload registers (TMR4RLH and TMR4RLL) is loaded into the Timer 4 register as shown in Figure 26.12,
and the Timer 4 High Byte Overflow Flag (TMR4CN.7) is set. If Timer 4 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 4 overflow. Additionally, if Timer 4 interrupts are enabled
and the TF4LEN bit is set (TMR4CN.5), an interrupt will be generated each time the lower 8 bits (TMR4L)
overflow from 0xFF to 0x00.
Figure 26.12. Timer 4 16-Bit Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
TMR4L TMR4H
TMR4RLL TMR4RLH
Reload
TCLK
0
1
TR4
TMR4CN
T4SPLIT
T4CSS
T4CE
TF4L
TF4H
T4XCLK
TR4
0
1
T4XCLK
Interrupt
TF4LEN
To ADC
CKCON1
T
4
M
L
T
4
M
H
T
5
M
L
T
5
M
H
C8051F380/1/2/3/4/5/6/7/C
289 Rev. 1.5
26.4.2. 8-bit Timers with Auto-Reload
When T4SPLIT is 1 and T4CE = 0, Timer 4 operates as two 8-bit timers (TMR4H and TMR4L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 26.13. TMR4RLL holds the reload value for
TMR4L; TMR4RLH holds the reload value for TMR4H. The TR4 bit in TMR4CN handles the run control for
TMR4H. TMR4L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 4 Clock Select bits (T4MH and T4ML in CKCON1) select either SYSCLK or
the clock defined by the Timer 4 External Clock Select bit (T4XCLK in TMR4CN), as follows:
The TF4H bit is set when TMR4H overflows from 0xFF to 0x00; the TF4L bit is set when TMR4L overflows
from 0xFF to 0x00. When Timer 4 interrupts are enabled, an interrupt is generated each time TMR4H over-
flows. If Timer 4 interrupts are enabled and TF4LEN (TMR4CN.5) is set, an interrupt is generated each
time either TMR4L or TMR4H overflows. When TF4LEN is enabled, software must check the TF4H and
TF4L flags to determine the source of the Timer 4 interrupt. The TF4H and TF4L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 26.13. Timer 4 8-Bit Mode Block Diagram
T4MH T4XCLK TMR4H Clock Source T4ML T4XCLK TMR4L Clock Source
0 0 SYSCLK/12 0 0 SYSCLK/12
0 1 External Clock/8 0 1 External Clock/8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1
TR4
External Clock / 8
SYSCLK / 12
0
1
T4XCLK
1
0
TMR4H
TMR4RLH
Reload
Reload
TCLK
TMR4L
TMR4RLL
Interrupt
TMR4CN
T4SPLIT
T4CSS
T4CE
TF4LEN
TF4L
TF4H
T4XCLK
TR4
To ADC
CKCON1
T
4
M
L
T
4
M
H
T
5
M
L
T
5
M
H
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 290
SFR Address = 0x91; SFR Page = F
SFR Definition 26.19. TMR4CN: Timer 4 Control
Bit76543210
Name
TF4H TF4L TF4LEN T4SPLIT TR4 T4XCLK
Type R/W R/W R/W R R/W R/W R R/W
Reset 00000000
Bit Name Function
7 TF4H Timer 4 High Byte Overflow Flag.
Set by hardware when the Timer 4 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 4 overflows from 0xFFFF to 0x0000. When the
Timer 4 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 4
interrupt service routine. This bit is not automatically cleared by hardware.
6 TF4L
Timer 4 Low Byte Overflow Flag.
Set by hardware when the Timer 4 low byte overflows from 0xFF to 0x00. TF4L will
be set when the low byte overflows regardless of the Timer 4 mode. This bit is not
automatically cleared by hardware.
5 TF4LEN
Timer 4 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 4 Low Byte interrupts. If Timer 4 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 4 overflows.
4 Unused Read = 0b; Write = don’t care.
3 T4SPLIT
Timer 4 Split Mode Enable.
When this bit is set, Timer 4 operates as two 8-bit timers with auto-reload.
0: Timer 4 operates in 16-bit auto-reload mode.
1: Timer 4 operates as two 8-bit auto-reload timers.
2TR4
Timer 4 Run Control.
Timer 4 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR4H only; TMR4L is always enabled in split mode.
1 Unused Read = 0b; Write = don’t care.
0T4XCLK
Timer 4 External Clock Select.
This bit selects the external clock source for Timer 4. However, the Timer 4 Clock
Select bits (T4MH and T4ML in register CKCON1) may still be used to select
between the external clock and the system clock for either timer.
0: Timer 4 clock is the system clock divided by 12.
1: Timer 4 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F380/1/2/3/4/5/6/7/C
291 Rev. 1.5
SFR Address = 0x92; SFR Page = F
SFR Address = 0x93; SFR Page = F
SFR Address = 0x94; SFR Page = F
SFR Definition 26.20. TMR4RLL: Timer 4 Reload Register Low Byte
Bit76543210
Name
TMR4RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR4RLL[7:0] Timer 4 Reload Register Low Byte.
TMR4RLL holds the low byte of the reload value for Timer 4.
SFR Definition 26.21. TMR4RLH: Timer 4 Reload Register High Byte
Bit76543210
Name
TMR4RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR4RLH[7:0] Timer 4 Reload Register High Byte.
TMR4RLH holds the high byte of the reload value for Timer 4.
SFR Definition 26.22. TMR4L: Timer 4 Low Byte
Bit76543210
Name
TMR4L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR4L[7:0] Timer 4 Low Byte.
In 16-bit mode, the TMR4L register contains the low byte of the 16-bit Timer 4. In
8-bit mode, TMR4L contains the 8-bit low byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 292
SFR Address = 0x95; SFR Page = F
SFR Definition 26.23. TMR4H Timer 4 High Byte
Bit76543210
Name
TMR4H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR4H[7:0] Timer 4 High Byte.
In 16-bit mode, the TMR4H register contains the high byte of the 16-bit Timer 4. In
8-bit mode, TMR4H contains the 8-bit high byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 293
26.5. Timer 5
Timer 5 is a 16-bit timer formed by two 8-bit SFRs: TMR5L (low byte) and TMR5H (high byte). Timer 5 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T5SPLIT bit (TMR5CN.3) defines
Timer 5 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system
clock.
26.5.1. 16-bit Timer with Auto-Reload
When T5SPLIT (TMR5CN.3) is zero, Timer 5 operates as a 16-bit timer with auto-reload. Timer 5 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 5
reload registers (TMR5RLH and TMR5RLL) is loaded into the Timer 5 register as shown in Figure 26.14,
and the Timer 5 High Byte Overflow Flag (TMR5CN.7) is set. If Timer 5 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 5 overflow. Additionally, if Timer 5 interrupts are enabled
and the TF5LEN bit is set (TMR5CN.5), an interrupt will be generated each time the lower 8 bits (TMR5L)
overflow from 0xFF to 0x00.
Figure 26.14. Timer 5 16-Bit Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
TMR5L TMR5H
TMR5RLL TMR5RLH
Reload
TCLK
0
1
TR5
TMR5CN
T5SPLIT
T5CSS
T5CE
TF5L
TF5H
T5XCLK
TR5
0
1
T5XCLK
Interrupt
TF5LEN
To ADC
CKCON1
T
4
M
L
T
4
M
H
T
5
M
L
T
5
M
H
C8051F380/1/2/3/4/5/6/7/C
294 Rev. 1.5
26.5.2. 8-bit Timers with Auto-Reload
When T5SPLIT is 1 and T5CE = 0, Timer 5 operates as two 8-bit timers (TMR5H and TMR5L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 26.15. TMR5RLL holds the reload value for
TMR5L; TMR5RLH holds the reload value for TMR5H. The TR5 bit in TMR5CN handles the run control for
TMR5H. TMR5L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 5 Clock Select bits (T5MH and T5ML in CKCON1) select either SYSCLK or
the clock defined by the Timer 5 External Clock Select bit (T5XCLK in TMR5CN), as follows:
The TF5H bit is set when TMR5H overflows from 0xFF to 0x00; the TF5L bit is set when TMR5L overflows
from 0xFF to 0x00. When Timer 5 interrupts are enabled, an interrupt is generated each time TMR5H over-
flows. If Timer 5 interrupts are enabled and TF5LEN (TMR5CN.5) is set, an interrupt is generated each
time either TMR5L or TMR5H overflows. When TF5LEN is enabled, software must check the TF5H and
TF5L flags to determine the source of the Timer 5 interrupt. The TF5H and TF5L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 26.15. Timer 5 8-Bit Mode Block Diagram
T5MH T5XCLK TMR5H Clock Source T5ML T5XCLK TMR5L Clock Source
0 0 SYSCLK/12 0 0 SYSCLK/12
0 1 External Clock/8 0 1 External Clock/8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1
TR5
External Clock / 8
SYSCLK / 12
0
1
T5XCLK
1
0
TMR5H
TMR5RLH
Reload
Reload
TCLK
TMR5L
TMR5RLL
Interrupt
TMR5CN
T5SPLIT
T5CSS
T5CE
TF5LEN
TF5L
TF5H
T5XCLK
TR5
To ADC
CKCON1
T
4
M
L
T
4
M
H
T
5
M
L
T
5
M
H
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 295
SFR Address = 0xC8; SFR Page = F; Bit-Addressable
SFR Definition 26.24. TMR5CN: Timer 5 Control
Bit76543210
Name
TF5H TF5L TF5LEN T5SPLIT TR5 T5XCLK
Type R/W R/W R/W R R/W R/W R R/W
Reset 00000000
Bit Name Function
7 TF5H Timer 5 High Byte Overflow Flag.
Set by hardware when the Timer 5 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 5 overflows from 0xFFFF to 0x0000. When the
Timer 5 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 5
interrupt service routine. This bit is not automatically cleared by hardware.
6 TF5L
Timer 5 Low Byte Overflow Flag.
Set by hardware when the Timer 5 low byte overflows from 0xFF to 0x00. TF5L will
be set when the low byte overflows regardless of the Timer 5 mode. This bit is not
automatically cleared by hardware.
5 TF5LEN
Timer 5 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 5 Low Byte interrupts. If Timer 5 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 5 overflows.
4 Unused Read = 0b; Write = don’t care.
3 T5SPLIT
Timer 5 Split Mode Enable.
When this bit is set, Timer 5 operates as two 8-bit timers with auto-reload.
0: Timer 5 operates in 16-bit auto-reload mode.
1: Timer 5 operates as two 8-bit auto-reload timers.
2TR5
Timer 5 Run Control.
Timer 5 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR5H only; TMR5L is always enabled in split mode.
1 Unused Read = 0b; Write = don’t care.
0T5XCLK
Timer 5 External Clock Select.
This bit selects the external clock source for Timer 5. However, the Timer 5 Clock
Select bits (T5MH and T5ML in register CKCON1) may still be used to select
between the external clock and the system clock for either timer.
0: Timer 5 clock is the system clock divided by 12.
1: Timer 5 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F380/1/2/3/4/5/6/7/C
296 Rev. 1.5
SFR Address = 0xCA; SFR Page = F
SFR Address = 0xCB; SFR Page = F
SFR Address = 0xCC; SFR Page = F
SFR Definition 26.25. TMR5RLL: Timer 5 Reload Register Low Byte
Bit76543210
Name
TMR5RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR5RLL[7:0] Timer 5 Reload Register Low Byte.
TMR5RLL holds the low byte of the reload value for Timer 5.
SFR Definition 26.26. TMR5RLH: Timer 5 Reload Register High Byte
Bit76543210
Name
TMR5RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR5RLH[7:0] Timer 5 Reload Register High Byte.
TMR5RLH holds the high byte of the reload value for Timer 5.
SFR Definition 26.27. TMR5L: Timer 5 Low Byte
Bit76543210
Name
TMR5L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR5L[7:0] Timer 5 Low Byte.
In 16-bit mode, the TMR5L register contains the low byte of the 16-bit Timer 5. In
8-bit mode, TMR5L contains the 8-bit low byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 297
SFR Address = 0xCD; SFR Page = F
SFR Definition 26.28. TMR5H Timer 5 High Byte
Bit76543210
Name
TMR5H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR5H[7:0] Timer 5 High Byte.
In 16-bit mode, the TMR5H register contains the high byte of the 16-bit Timer 5. In
8-bit mode, TMR5H contains the 8-bit high byte timer value.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 298
27. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Fre-
quency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in Section “27.3. Capture/Compare
Modules” on page 301). The external oscillator clock option is ideal for real-time clock (RTC) functionality,
allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the sys-
tem clock. The PCA is configured and controlled through the system controller's Special Function Regis-
ters. The PCA block diagram is shown in Figure 27.1
Important Note: The PCA Module 4 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset.
Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 27.4 for details.
Figure 27.1. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0
Capture/Compare
Module 2
CEX1
ECI
Crossbar
CEX2
CEX0
Port I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 3
Capture/Compare
Module 4 / WDT
CEX3
CEX4
C8051F380/1/2/3/4/5/6/7/C
299 Rev. 1.5
27.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 27.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Figure 27.2. PCA Counter/Timer Block Diagram
Table 27.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
0 0 0 System clock divided by 12
0 0 1 System clock divided by 4
0 1 0 Timer 0 overflow
011
High-to-low transitions on ECI (max rate = system clock divided
by 4)
1 0 0 System clock
1 0 1 External oscillator source divided by 8
*
11xReserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
4
C
C
F
3
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
IDLE
0
1
PCA0H PCA0L
Snapshot
Register
To SFR Bus
Overflow
To PCA Interrupt System
CF
PCA0L
read
To PCA Modules
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
000
001
010
011
100
101
SYSCLK
External Clock/8
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 300
27.2. PCA0 Interrupt Sources
Figure 27.3 shows a diagram of the PCA interrupt tree. There are six independent event flags that can be
used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon
a 16-bit overflow of the PCA0 counter and the individual flags for each PCA channel (CCF0, CCF1, CCF2,
CCF3, and CCF4), which are set according to the operation mode of that module. These event flags are
always set when the trigger condition occurs. Each of these flags can be individually selected to generate
a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, and ECCFn for each CCFn).
PCA0 interrupts must be globally enabled before any individual interrupt sources are recognized by the
processor. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1.
Figure 27.3. PCA Interrupt Block Diagram
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
4
C
C
F
3
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
0
1
PCA Module 0
(CCF0)
PCA Module 1
(CCF1)
ECCF1
0
1
ECCF0
0
1
PCA Module 2
(CCF2)
ECCF2
PCA Counter/Timer 16-
bit Overflow
0
1
Interrupt
Priority
Decoder
EPCA0
0
1
EA
0
1
PCA0CPMn
(for n = 0 to 4)
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
1
PCA Module 3
(CCF2)
ECCF3
0
1
PCA Module 4
(CCF2)
ECCF4
C8051F380/1/2/3/4/5/6/7/C
301 Rev. 1.5
27.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high-speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse
width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 sys-
tem controller. These registers are used to exchange data with a module and configure the module's mode
of operation. Table 27.2 summarizes the bit settings in the PCA0CPMn register used to select the PCA
capture/compare module’s operating mode. Setting the ECCFn bit in a PCA0CPMn register enables the
module's CCFn interrupt.
Table 27.2. PCA0CPM Bit Settings for PCA Capture/Compare Modules
Operational Mode PCA0CPMn
Bit Number76543210
Capture triggered by positive edge on CEXn XX10000A
Capture triggered by negative edge on CEXn XX01000A
Capture triggered by any transition on CEXn XX11000A
Software Timer XB00100A
High Speed Output XB00110A
Frequency Output XB00011A
8-Bit Pulse Width Modulator 0 B 0 0 C 0 1 A
16-Bit Pulse Width Modulator 1 B 0 0 C 0 1 A
Notes:
1.
X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = When set to 0, the digital comparator is off. For high speed and frequency output modes, the associated
pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
4. C = When set, a match event will cause the CCFn flag for the associated channel to be set.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 302
27.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Figure 27.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
PCA0L
PCA0CPLn
PCA
Timebase
CEXn
CrossbarPort I/O
PCA0H
Capture
PCA0CPHn
0
1
0
1
(to CCFn)
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
4
C
C
F
3
PCA Interrupt
x 000xx
C8051F380/1/2/3/4/5/6/7/C
303 Rev. 1.5
27.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 27.5. PCA Software Timer Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
00 00
0
1
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
4
C
C
F
3
PCA Interrupt
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 304
27.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the
next match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 27.6. PCA High-Speed Output Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
0
1
00 0x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
CEXn
Crossbar Port I/O
Toggle
0
1
TOGn
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
4
C
C
F
3
PCA Interrupt
C8051F380/1/2/3/4/5/6/7/C
305 Rev. 1.5
27.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the
output is toggled. The frequency of the square wave is then defined by Equation 27.1.
Equation 27.1. Square Wave Frequency Output
Where F
PCA
is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
Figure 27.7. PCA Frequency Output Mode
F
CEXn
F
PCA
2PCA0CPHn
-------------------------------------------=
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
8-bit
Comparator
PCA0L
Enable
PCA Timebase
match
PCA0CPHn8-bit AdderPCA0CPLn
Adder
Enable
CEXn
Crossbar Port I/O
Toggle
0
1
TOGn
000 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 306
27.3.5. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 27.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag
for the module will be set each time an 8-bit comparator match (rising edge) occurs. The duty cycle for 8-
Bit PWM Mode is given in Equation 27.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 27.2. 8-Bit PWM Duty Cycle
Using Equation 27.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 27.8. PCA 8-Bit PWM Mode Diagram
Duty Cycle
256 PCA0CPHn
–
256
-------------------------------------------------------=
8-bit
Comparator
PCA0L
PCA0CPLn
PCA0CPHn
CEXn
Crossbar Port I/O
Enable
Overflow
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
COVF
C8051F380/1/2/3/4/5/6/7/C
307 Rev. 1.5
27.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod-
ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is asserted high; when the 16-bit counter overflows, CEXn is
asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn
match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the
PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn
= 1) to help synchronize the capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for
the module will be set each time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN
can be used to detect the overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by
Equation 27.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 27.3. 16-Bit PWM Duty Cycle
Using Equation 27.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 27.9. PCA 16-Bit PWM Mode
Duty Cycle
65536 PCA0CPn
–
65536
---------------------------------------------------------=
PCA0CPLnPCA0CPHn
Enable
PCA Timebase
00x0 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
1
16-bit Comparator
CEXn
Crossbar Port I/O
Overflow
Q
Q
SET
CLR
S
R
match
PCA0H PCA0L
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 308
27.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Mod-
ule 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be
used when WDT updates are performed.
The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled.
The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
27.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 4 is forced into software timer mode.
Writes to the Module 4 mode register (PCA0CPM4) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is
loaded into PCA0CPH4 (See Figure 27.10).
Figure 27.10. PCA Module 4 with Watchdog Timer Enabled
PCA0H
Enable
PCA0L Overflow
Reset
PCA0CPL4 8-bit Adder
PCA0CPH4
Adder
Enable
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
Match
Write to
PCA0CPH4
8-bit
Comparator
C8051F380/1/2/3/4/5/6/7/C
309 Rev. 1.5
The 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This offset
value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first
PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The total off-
set is then given (in PCA clocks) by Equation 27.4, where PCA0L is the value of the PCA0L register at the
time of the update.
Equation 27.4. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF4 flag (PCA0CN.4) while the WDT is
enabled.
27.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
1. Disable the WDT by writing a 0 to the WDTE bit.
2. Select the desired PCA clock source (with the CPS2
–CPS0 bits).
3. Load PCA0CPL4 with the desired WDT update offset value.
4. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
5. Enable the WDT by setting the WDTE bit to 1.
6. Reset the WDT timer by writing to PCA0CPH4.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 27.4, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 27.3 lists some example tim-
eout intervals for typical system clocks.
Offset 256 PCA0CPL4256 PCA0L–+=
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 310
Table 27.3. Watchdog Timer Timeout Intervals
1
System Clock (Hz) PCA0CPL4 Timeout Interval (ms)
48,000,000 255 16.4
48,000,000 128 8.3
48,000,000 32 2.1
12,000,000 255 65.5
12,000,000 128 33.0
12,000,000 32 8.4
1,500,000
2
255 524.3
1,500,000
2
128 264.2
1,500,000
2
32 67.6
32,768 255 24,000
32,768 128 12,094
32,768 32 3,094
Notes:
1.
Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
C8051F380/1/2/3/4/5/6/7/C
311 Rev. 1.5
27.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Address = 0xD8; SFR Page = All Pages; Bit-Addressable
SFR Definition 27.1. PCA0CN: PCA Control
Bit76543210
Name
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
Type R/W R/W R R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CFPCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5 Unused Read = 0b, Write = Don't care.
2 CCF4
PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
1 CCF3
PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
2 CCF2
PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
1 CCF1
PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
0 CCF0
PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 312
SFR Address = 0xD9; SFR Page = All Pages
SFR Definition 27.2. PCA0MD: PCA Mode
Bit76543210
Name
CIDL WDTE WDLCK CPS[2:0] ECF
Type R/W R/W R/W R R/W R/W
Reset 01000000
Bit Name Function
7CIDLPCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6WDTE
Watchdog Timer Enable.
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
5 WDLCK
Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4 Unused Read = 0b, Write = Don't care.
3:1 CPS[2:0]
PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
0ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
C8051F380/1/2/3/4/5/6/7/C
313 Rev. 1.5
SFR Addresses: 0xDA (n = 0), 0xDB (n = 1), 0xDC (n = 2), 0xDD (n = 3), 0xDE (n = 4)
SFR Pages: All Pages (n = 0), All Pages (n = 1), All Pages (n = 2), All Pages (n = 3), All Pages (n = 4)
SFR Definition 27.3. PCA0CPMn: PCA Capture/Compare Mode
Bit76543210
Name
PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PWM16n16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8-bit PWM selected.
1: 16-bit PWM selected.
6ECOMn
Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
5 CAPPn
Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4 CAPNn
Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2TOGn
Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1PWMn
Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n
is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is also set,
the module operates in Frequency Output Mode.
0ECCFn
Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM4 register cannot be modified, and module 4 acts as the
watchdog timer. To change the contents of the PCA0CPM4 register or the function of module 4, the Watchdog
Timer must be disabled.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 314
SFR Address = 0xF9; SFR Page = All Pages
SFR Address = 0xFA; SFR Page = All Pages
SFR Definition 27.4. PCA0L: PCA Counter/Timer Low Byte
Bit76543210
Name
PCA0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 27.5. PCA0H: PCA Counter/Timer High Byte
Bit76543210
Name
PCA0[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 27.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
C8051F380/1/2/3/4/5/6/7/C
315 Rev. 1.5
SFR Addresses: 0xFB (n = 0), 0xE9 (n = 1), 0xEB (n = 2), 0xED (n = 3), 0xFD (n = 4)
SFR Pages: All Pages (n = 0), All Pages (n = 1), All Pages (n = 2), All Pages (n = 3), All Pages (n = 4)
SFR Addresses: 0xFC (n = 0), 0xEA (n = 1), 0xEC (n = 2), 0xEE (n = 3), 0xFE (n = 4)
SFR Pages: All Pages (n = 0), All Pages (n = 1), All Pages (n = 2), All Pages (n = 3), All Pages (n = 4)
SFR Definition 27.6. PCA0CPLn: PCA Capture Module Low Byte
Bit76543210
Name
PCA0CPn[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 27.7. PCA0CPHn: PCA Capture Module High Byte
Bit76543210
Name
PCA0CPn[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[15:8]
PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
Note: A write to this register will set the module’s ECOMn bit to a 1.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 316
28. C2 Interface
C8051F380/1/2/3/4/5/6/7/C devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow
Flash programming and in-system debugging with the production part installed in the end application. The
C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information
between the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
28.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 inter-
face. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 28.1. C2ADD: C2 Address
Bit76543210
Name
C2ADD[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
Address Description
0x00 Selects the Device ID register for Data Read instructions
0x01 Selects the Revision ID register for Data Read instructions
0x02 Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xAD Selects the C2 Flash Programming Data register for Data
Read/Write instructions
C8051F380/1/2/3/4/5/6/7/C
317 Rev. 1.5
C2 Address: 0x00
C2 Address: 0x01
C2 Register Definition 28.2. DEVICEID: C2 Device ID
Bit76543210
Name
DEVICEID[7:0]
Type R/W
Reset 00101000
Bit Name Function
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x28
(C8051F380/1/2/3/4/5/6/7/C).
C2 Register Definition 28.3. REVID: C2 Revision ID
Bit76543210
Name
REVID[7:0]
Type R/W
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 318
C2 Address: 0x02
C2 Address: 0xAD
C2 Register Definition 28.4. FPCTL: C2 Flash Programming Control
Bit76543210
Name
FPCTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the following codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 28.5. FPDAT: C2 Flash Programming Data
Bit76543210
Name
FPDAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code Command
0x06 Flash Block Read
0x07 Flash Block Write
0x08 Flash Page Erase
0x03 Device Erase
C8051F380/1/2/3/4/5/6/7/C
319 Rev. 1.5
28.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely ‘borrow’ the C2CK (RST
) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 28.1.
Figure 28.1. Typical C2 Pin Sharing
The configuration in Figure 28.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST
pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
C2D
C2CK
RST (a)
Input (b)
Output (c)
C2 Interface Master
C8051Fxxx
C8051F380/1/2/3/4/5/6/7/C
Rev. 1.5 320
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 1.0
Updated Electrical Characteristics tables with latest data: Table 4.2, Table 4.4, Table 4.5, Table 4.7,
Table 4.8, Table 4.10, Table 4.11 and Table 4.12.
Changed bit REG01CN.5 to Reserved in SFR Definition 8.1 and updated corresponding descriptions in
sections 16.9 and 18.3.1.
Updated Figure 18.1. Oscillator Options.
Changed SFR Page in SFR Definition 21.2.
Updated descriptions of XOSCMD for Capacitor and RC modes in SFR Definition 18.6.
Revision 1.0 to Revision 1.1
Updated front-page diagram to reflect the correct number of Timers, 6 instead of 4.
Updated Table 3.2, “TQFP-48 Package Dimensions,” on page 26 with the following:
Fixed right-most column name from Min to Max
Added max values for dimensions A, A1, A2, b, c, L, and q
Updated Figure 3.8 and Table 3.6 with correct QFN-32 package drawing and dimensions.
Updated Table 5.10, “ADC0 Electrical Characteristics,” on page 42 with new maximum value for ADC0
Power Supply Current. This addresses an item from the May 18th, 2012 Errata.
Added Section 6.2 regarding the Temperature Sensor.
Removed references to programmable gain in “6. 10-Bit ADC (ADC0, C8051F380/1/2/3/C only)” .
Updated Table 15.1, “Special Function Register (SFR) Memory Map,” on page 112 to fill in the missing
row information for the 0xC8 row.
Updated Table 16.1, “Interrupt Summary,” on page 120. The TMR4CN register is not bit-addressable.
Updated definition for the 000b value of the CLKSL bits in SFR Definition 19.1 (CLKSEL) to include the
/4 factor.
Revision 1.1 to Revision 1.2
Updated Comparator Input Offset Voltage specification in Table 5.13 on page 44.
Revision 1.2 to Revision 1.3
Added VBUS to Table 5.1, “Absolute Maximum Ratings,” on page 37.
Added the “4. Typical Connection Diagrams” chapter.
Removed Figure 8.1, Figure 8.2, Figure 8.3, and Figure 8.4. These figures were replaced with a
reference to the “4. Typical Connection Diagrams” chapter.
Revision 1.3 to Revision 1.4
Added new device C8051F38C.
Updated Flash Endurance minimum specification, Flash Erase Cycle Time maximum specification, and
added a note to Table 5.6 on page 40.
Updated Figure 22.1 to show proper clock sources for SMBus0 and SMBus1.
Revision 1.4 to Revision 1.5
Added required settings for operation above 25 MHz in “12. Prefetch Engine” on page 88.
Simplicity Studio
One-click access to MCU and
wireless tools, documentation,
software, source code libraries &
more. Available for Windows,
Mac and Linux!
IoT Portfolio
www.silabs.com/IoT
SW/HW
www.silabs.com/simplicity
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
http://www.silabs.com
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.
Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the
performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant
any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket
approval is required or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or
health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon
Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering
such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such
unauthorized applications.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, Gecko
OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® , Zentri, the Zentri logo and Zentri DMS, Z-Wave®,
and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered
trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance. All other products or brand names mentioned herein are trademarks of their respective holders.
